M16CSLASH29 datasheet(289/499 Pages) RENESAS

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16. MULTI-MASTER I2C bus INTERFACE

page 265

16.3 I2C0 Clock Control Register (S20 register)

The S20 register is used to set theACK control, SCL mode and the SCL frequency.

16.3.1 Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4)

These bits control the SCL frequency. See Table 16.3 .

16.3.2 Bit 5: SCL Mode Specification Bit (FAST MODE)

The FAST MODE bit selects SCL mode. When the FAST MODE bit is set to 0, standard clock mode

is entered. When it is set to 1, high-speed clock mode is entered.

When using the high-speed clock mode I2C bus standard (400 kbit/s maximum) to connect buses, set

the FAST MODE bit to 1 (select SCL mode as high-speed clock mode) and use the I2C bus system

clock (VIIC) at 4 MHz or more frequency.

16.3.3 Bit 6: ACK Bit (ACKBIT)

The ACKBIT bit sets the SDA status when an ACK clock(1) is generated. When the ACKBIT bit is set

to 0, ACK is returned and te clock applied to SDA becomes "L" when ACK clock is generated. When

it is set to 1, ACK is not returned and the clock clock applied to SDA maintains "H" at ACK clock

generation.

When the ACKBIT bit is set to 0, the address data is received. When the slave address matches with

the address data, SDA becomes "L" automatically (ACK is returned). When the slave address and the

address data are not matched, SDA becomes "H" (ACK is not returned).

NOTE:

1. ACK clock: Clock for acknowledgment

16.3.4 Bit 7: ACK Clock Bit (ACK-CLK)

The ACK-CLK bit set a clock for data transfer acknowledgement. When the ACK-CLK bit is set to 0,

ACK clock is not generated after data is transferred. When it is set to 1, a master generates ACK clock

every one-bit data transfer is completed. The device, which transmits address data and control data,

leave SDA pin open (apply "H" signal to SDA) when ACK clock is generated. The device which

receives data, receives the generated ACKBIT bit.

NOTE:

1.Do not rewrite the S20 register, other than the ACKBIT bit during data transfer. If data is written

to other than the ACKBIT bit during transfer, the I2C bus clock circuit is reset and the data may

not be transferred successfully.

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