M16CSLASH29 datasheet(294/499 Pages) RENESAS

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16. MULTI-MASTER I2C bus INTERFACE

page 270

16.5.5 Bit 4: I2C bus Interface Interrupt Request Bit (PIN)

The PIN bit generates an I2C bus interface interrupt request signal. Every one byte data is ransferred, the

PIN bit is changed from 1 to 0. At the same time, an I2C bus interface interrupt request is generated. The

PIN bit is synchronized with the last clock of the internal transfer clock (when ACK-CLK=1, the last clock

is the ACK clock: when the ACK-CLK=0, the last clock is the 8th clock) and it becomes 0. The interrupt

request is generated on the falling edge of the PIN bit. When the PIN bit is set to 0, the clock applied to

SCL maintains "L" and further clock generation is disabled. When the ACK-CLK bit is set to 1 and the

WIT bit in the S3D0 register is set to 1 (enable the I2C bus interface interrupt of data receive completion).

The PIN bit is synchronized with the last clock and the falling edge of the ACK clock. Then, the PIN bit is

set to 0 and I2C bus interface interrupt request is generated. Figure 16.11 shows the timing of the I2C

bus interface interrupt request generation.

The PIN bit is set to 1 in one of the following conditions:

•When data is written to the S00 register

•When data is written to the S20 register (when the WIT bit is set to 1 and the internal WAIT flag is set

to 1)

•When the ES0 bit in the S1D0 register is set to 0 (I2C bus interface disabled)

•When the IHR bit in the S1D0 register is set to 1(reset)

The PIN bit is set to 0 in one of the following conditions:

•With completion of 1-byte data transmit (including a case when arbitration lost is detected)

•With completion of 1-byte data receive

•When the ALS bit in the S1D0 register is set to 0 (addressing format) and slave address is matched

or general call address is received successfully in slave receive mode

•When the ALS bit is set to 1 (free format) and the address data is received successfully in slave

receive mode

16.5.6 Bit 5: Bus Busy Flag (BB)

The BB flag indicates the operating conditions of the bus system. When the BB flag is set to 0, a bus

system is not in use and a START condition can be generated. The BB flag is set and reset based on an

input signal of the SCL and SDA pins either in master mode or in slave mode. When the START condition

is detected, the BB flag is set to 1. On the other hand, when the STOP condition is detected, the BB flag

is set to 0. Bits SSC4 to SSC0 in the S2D0 register decide to detect between the START condition and

the STOP condition. When the ES0 bit in the S1D0 register is set to 0 (I2C bus interface disabled) or

when the IHR bit in the S1D0 register is set to 1 (reset), the BB flag is set to 0. Refer to 16.9 START

Condition Generation Method and 16.11 STOP Condition Generation Method

Figure 16.11 Interrupt request signal generation timing

SCL

PIN flag

I2CIRQ

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