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M16C/29 датащи(PDF) 232 Page - Renesas Technology Corp |
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M16C/29 датащи(HTML) 232 Page - Renesas Technology Corp |
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232 / 499 page ![]() 14. Serial I/O p u o r G 9 2 / C 6 1 M page 208 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R 14.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the U2SMR3 register and the CKPOL bit in the U2C0 register. Make sure the transfer clock polarity and phase are the same for the master and slave to communi- cate. 14.1.4.1.1 Master (Internal Clock) Figure 14.27 shows the transmission and reception timing in master (internal clock). 14.1.4.1.2 Slave (External Clock) Figure 14.28 shows the transmission and reception timing (CKPH=0) in slave (external clock) while Figure 14.29 shows the transmission and reception timing (CKPH=1) in slave (external clock). Figure 14.27 Transmission and Reception Timing in Master Mode (Internal Clock) Data output timing Data input timing D0 D1 D2 D3 D4 D6 D7 D5 Clock output (CKPOL=0, CKPH=0) "H" "L" Clock output (CKPOL=1, CKPH=0) "H" "L" Clock output (CKPOL=0, CKPH=1) "H" "L" Clock output (CKPOL=1, CKPH=1) "H" "L" "H" "L" |
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