M16CSLASH29 datasheet(229/499 Pages) RENESAS

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14. Serial I/O

page 205

14.1.3.7 ACK and NACK

If the STSPSEL bit in the U2SMR4 register is set to 0 (start and stop conditions not generated) and the

ACKC bit in the U2SMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the

U2SMR4 register is output from the SDA2 pin.

If the IICM2 bit is set to 0, a NACK interrupt request is generated if the SDA2 pin remains high at the

rising edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDA2 pin

is low at the rising edge of the 9th bit of transmit clock pulse.

If ACK2 is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an

acknowledge.

14.1.3.8 Initialization of Transmission/Reception

If a start condition is detected while the STAC bit is set to 1 (UART2 initialization enabled), the serial I/

O operates as described below.

- The transmit shift register is initialized, and the content of the U2TB register is transferred to the

transmit shift register. In this way, the serial I/O starts sending data synchronously with the next clock

pulse applied. However, the UART2 output value does not change state and remains the same as

when a start condition was detected until the first bit in the data is output synchronously with the input

clock.

- The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the

next clock pulse applied.

- The SWC bit is set to 1 (SCL2 wait output enabled). Consequently, the SCL2 pin is pulled low at the

falling edge of the ninth clock pulse.

Note that when UART2 transmission/reception is started using this function, the TI does not change

state. Note also that when using this function, the selected transfer clock should be an external clock.

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