M16CSLASH29 datasheet(227/499 Pages) RENESAS

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14. Serial I/O

page 203

Table 14.14 STSPSEL Bit Functions

Figure 14.25 STSPSEL Bit Functions

Function

Output of SCL2 and SDA2 pins

Start/stop condition interrupt

request generation timing

STSPSEL = 0

Output transfer clock and data/

Program with a port determines

how the start condition or stop

condition is output

Start/stop condition are detec-

ted

STSPSEL = 1

The STAREQ, RSTAREQ and

STPREQ bit determine how the

start condition or stop condition is

output

Start/stop condition generation

are completed

14.1.3.3 Arbitration

Unmatching of the transmit data and SDA2 pin input data is checked synchronously with the rising

edge of SCL2. Use the ABC bit in the U2SMR register to select the timing at which the ABT bit in the

U2RB register is updated. If the ABC bit is set to 0 (updated bitwise), the ABT bit is set to 1 at the same

time unmatching is detected during check, and is cleared to 0 when not detected. In cases when the

ABC bit is set to 1, if unmatching is detected even once during check, the ABT bit is set to 1

(unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be

updated bytewise, clear the ABT bit to 0 (undetected) after detecting acknowledge in the first byte,

before transferring the next byte.

Setting the ALS bit in the U2SMR2 register to 1 (SDA2 output stop enabled) causes arbitration-lost to

occur, in which case the SDA2 pin is placed in the high-impedance state at the same time the ABT bit

is set to 1 (unmatching detected).

SDA2

(1) In slave mode,

CKDIR is set to 1 (external clock)

SCL2

SDA2

Start condition detection

interrupt

Stop condition detection

interrupt

(2) In master mode,

CKDIR is set to 0 (internal clock), CKPH is set to 1(clock delayed)

SCL2

Set STAREQ

to 1 (start)

Set STPREQ

to 1 (start)

STPSEL bit

Set to 1 by

program

Set to 0 by

program

Set to 1 by

program

Set to 0 by

program

1st

2nd 3rd

5th

6th

7th

8th

9th bit

1st

2nd 3rd

5th

6th 7th

8th 9th bit

4th

Start condition detection

interrupt

Stop condition detection

interrupt

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