M16CSLASH29 datasheet(463/499 Pages) RENESAS

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22. Usage Notes

page 439

MCU

VCC

VSS

AVCC

AVSS

VREF

ANi

VCC

NOTES:

1. C1 ≥ 0.47 µF, C2 ≥ 0.47 µF, C3 ≥ 100 pF, C4 ≥ 0.1 µF (reference)

2. Use thick and shortest possible wiring to connect capacitors.

ANi: ANi, AN0i, AN2i (i=0 to 7), and AN3i (i=0 to 2)

22.9 A/D Converter

1. Set registers ADCON0 (except bit 6), ADCON1, ADCON2 and ADTRGCON when A/D conversion is

stopped (before a trigger occurs).

2. When the VCUT bit in ADCON1 register is changed from 0 (Vref not connected) to 1 (Vref connected),

start A/D conversion after passing 1 µs or longer.

3. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert

capacitors between the AVCC, VREF, and analog input pins (ANi, AN0i, AN2i(i=0 to 7), and AN3i(i=0 to

2)) each and the AVSS pin. Similarly, insert a capacitor between the VCC1 pin and the VSS pin. Figure

22.4

is an example connection of each pin.

4. Make sure the port direction bits for those pins that are used as analog inputs are set to 0 (input mode).

Also, if the TGR bit in the ADCON0 register is set to 1 (external trigger), make sure the port direction bit

___________

for the ADTRG pin is set to 0 (input mode).

When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key

input interrupt request is generated when the A/D input voltage goes low.)

6. The φAD frequency must be 10 MHz or less. Without sample-and-hold function, limit the φAD frequency

to 250kHZ or more. With the sample and hold function, limit the φAD frequency to 1MHZ or more.

7. When changing an A/D operation mode, select analog input pin again in bits CH2 to CH0 in the

ADCON0 register and bits SCAN1 to SCAN0 in the ADCON1 register.

Figure 22.4 Use of capacitors to reduce noise

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