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M16C/29 датащи(PDF) 467 Page - Renesas Technology Corp |
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M16C/29 датащи(HTML) 467 Page - Renesas Technology Corp |
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467 / 499 page ![]() p u o r G 9 2 / C 6 1 M 22. Usage Notes page 443 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R Figure 22.5 When Updating Period of CAN Module Matches Access Period from CPU Figure 22.6 With a Wait Time of 3fCAN Before CPU Read Figure 22.7 When Polling Period of CPU is 3fCAN or Longer fCAN ✕ : When the CAN module’s State_Reset bit updating period matches the CPU’s read period, it does not enter reset mode, for the CPU read has the higher priority. ✕✕ ✕ ✕✕ CPU read signal CPU reset signal Updating period of CAN module C0STR register b8: State_Reset bit 0: CAN operation mode 1: CAN reset/initial- ization mode : Updated without fail in period of 3fCAN CPU read signal CPU reset signal Updating period of the CAN module C0STR register b8: State_Reset bit Wait time 0: CAN operation mode 1: CAN reset/initial- ization mode CPU read signal CPU reset signal Updating period of the CAN module C0STR register b8: State_Reset bit ✕ 4fCAN 0: CAN operation mode 1: CAN reset/initial- ization mode : Updated without fail in period of 4fCAN ✕ : When the CAN module’s State_Reset bit updating period matches the CPU’s read period, it does not enter reset mode, for the CPU read has the higher priority. |
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