M16CSLASH29 datasheet(460/499 Pages) RENESAS

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22. Usage Notes

page 436

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22.7.2 Rewrite the ICOCiIC Register

When the interrupt request to the ICOCiIC register is generated during the instruction process, the IR bit

may not be set to 1 (interrupt requested) and the interrupt request may not be acknowledged. At that time,

when the bit in the G1IR register is held to 1 (interrupt requested), the following IC/OC interrupt request

will not be generated. When changing the ICOCiIC register settiing, use the following instruction.

Subject instructions: AND, OR, BCLR, BSET

When initializing Timer S, change the ICOCiIC register setting with the request again after setting regis-

ters IOCiIC and G1IR to 0016.

22.7.3 Waveform Generating Function

1. If the BTS bit in the G1BCR1 register is set to 0 (base timer is reset) when the waveform is generating

and the base timer is stopped counting, the waveform output pin keeps the same output level. The output

level will be changed when the base timer and the G1POj register match the setting value next time after

the base timer starts counting again.

2. If the G1POCRj register is set when the waveform is generated, the same setting value of the IVL bit is

applied to the waveform generating pin. Do not set the G1POCRj register when the waveform is generat-

ing.

3. When the RST1 bit in the G1BCR1 register is set to 1 (the base timer is reset by matching the G1PO0

G1PO0 register value. A high-level ("H") signal is applied to the OUTC10 pin between the base timer

value match to the base timer reset.

22.7.4 IC/OC Base Timer Interrupt

If the MCU is operated in the combination selected from Table 22.1 for use when the RST4 bit in the

G1BCR0 register is set to 1 (reset the base timer that matches the G1BTRR register) to reset the base

timer, an IC/OC base timer interrupt request is generated twice.

Table 22.1 Uses of IT Bit in the G1BCR0 Register and G1BTRR Register

The second IC/OC base timer interrupt request is generated because the base timer overflow request is

generated after one fBT1 clock cycle as soon as the base timer is reset.

One of the following conditions must be met in order not to generate the IC/OC base timer interrupt

request twice:

1) When the RST4 bit is set to 1, set the G1BTRR register with a combination other than what is listed in

Table 22.1

2) Do not reset the base timer by matching the G1BTRR register. Reset the base timer by matching the

G1P00 register. In other words, do not set the RST4 bit to 1 to reset the base timer. Set the RST1 bit in

the G1BCR1 register to 1 (reset the base timer that matches the G1P00 register).

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