M16CSLASH29 datasheet(461/499 Pages) RENESAS

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22. Usage Notes

page 437

22.8 Serial I/O

22.8.1 Clock-Synchronous Serial I/O

22.8.1.1 Transmission/reception

_______

________

1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin

goes to “L” when the data-receivable status becomes ready, which informs the transmission side

________

that the reception has become ready. The output level of the RTSi pin goes to “H” when reception

________

starts. So if the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can

_______

transmission and reception data with consistent timing. With the internal clock, the RTS function

has no effect.

_____

2. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to 1

_____

(three-phase output forcible cutoff by input on SD pin enabled), the P73/RTS2/TxD1(when the

U1MAP bit in PACR register is 1) and CLK2 pins go to a high-impedance state.

22.8.1.2 Transmission

When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0

edge of the transfer clock), the external clock is in the high state; if the CKPOL bit in the UiC0 register

is set to 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the

transfer clock), the external clock is in the low state.

• The TE bit in UiC1 register is set to 1 (transmission enabled)

• The TI bit in UiC1 register is set to 0 (data present in UiTB register)

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• If CTS function is selected, input on the CTSi pin is set to “L”

22.8.1.3 Reception

1. In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix

settings for transmission even when using the device only for reception. Dummy data is output to

the outside from the TxDi pin when receiving data.

2. When an internal clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to 1 (transmission

enabled) and write dummy data to the UiTB register, and the shift clock will thereby be generated.

When an external clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to 1 and write dummy

data to the UiTB register, and the shift clock will be generated when the external clock is fed to the CLKi

input pin.

3. When successively receiving data, if all bits of the next receive data are prepared in the UARTi

receive register while the RE bit in the UiC1 register (i = 0 to 2) is set to 1 (data present in the UiRB

In this case, because the content of the UiRB register is undefined, a corrective measure must be

taken by programs on the transmit and receive sides so that the valid data before the overrun error

occurred will be retransmitted. Note that when an overrun error occurred, the SiRIC register IR bit

does not change state.

4. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every

time reception is made.

5. When an external clock is selected, make sure the external clock is in high state if the CKPOL bit is

set to 0, and in low state if the CKPOL bit is set to 1 before the following conditions are met:

• The RE bit in the UiC1 register is set to 1 (reception enabled)

• The TE bit in the UiC1 register is set to 1 (transmission enabled)

• The TI bit in the UiC1 register= 0 (data present in the UiTB register)

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