7547 datasheet(11/91 Pages) RENESAS

11 / 91 page

Rev.1.21

Nov 15, 2006

page 11 of 89

REJ03B0156-0121

7547 Group

Fig. 8 Switching method of CPU mode register

Fig. 7 Structure of CPU mode register

Oscillation mode selection bit (Note 1, Note 4)

0 : Ceramic oscillation

1 : RC oscillation

CPU mode register (Note 1)

(CPUM: address 003B16, initial value: 8016)

Stack page selection bit

0 : 0 page

1 : 1 page

Clock division ratio selection bits

b7 b6

0 : f(

φ) = f(XIN)/2 (High-speed mode)

1 : f(

φ) = f(XIN)/8 (Middle-speed mode)

0 : applied from on-chip oscillator

1 : f(

φ) = f(XIN)/1 (Double-speed mode)(Note 5)

On-chip oscillator oscillation control bit (Note 3)

0 : On-chip oscillator oscillation enabled

1 : On-chip oscillator oscillation stop

XIN oscillation control bit

0 : Ceramic or RC oscillation enabled

1 : Ceramic or RC oscillation stop

Processor mode bits

b1 b0

0 Single-chip mode

1 Not available

0 Not available

1 Not available

Note 1: When the setting by the function set ROM data 2 (FSROM2) is performed, the initial value of CPUM is changed

after releasing reset since bit 5 of CPUM is fixed.

2: The setting values of FSROM2 become valid by setting “0” to bit 0 of function set ROM data 0 (FSROM0).

The setting values of FSROM2 are invalid by setting “1” to this bit.

(In order that FSROM2 is invalid, write to CPUM after releasing reset.)

3: When bit 4 of FSROM2 is set to “0”, the operation of on-chip oscillator cannot be stopped.

Since the on-chip oscillator is not stopped also in the stop mode, the dissipation current in the stop mode is increased.

4: The setting value of bit 5 of CPUM can be fixed after releasing reset by setting value of bit 5 of FSROM2.

Also, when the setting of FSROM2 is invalid, this bit can be rewritten only once after releasing reset.

After rewriting it is disable to write any data to this bit.

This bit is initialized by reset, and then, rewriting it is enabled.

5: This setting can be used only at ceramic oscillation. Do not use this at RC oscillation.

Control by Function set ROM data 2

(FSROM2: address FFDA16) (Note 2)

This bit function can be set by setting bit 5 of FSROM2. (Note 4)

Bit 5 of FSROM2 = 0: Bit 5 of CPUM is fixed to “0”.

Bit 5 of FSROM2 = 1: Bit 5 of CPUM is “0” or “1”.

This cannot be controlled by FSROM2.

This bit function can be set by setting bit 4 of FSROM2. (Note 3)

Bit 4 of FSROM2 = 0: Bit 3 of CPUM is fixed to “0”.

Bit 4 of FSROM2 = 1: Bit 3 of CPUM is “0” or “1”.

This cannot be controlled by FSROM2.

After releasing reset

Switch the oscillation mode

selection bit (bit 5 of CPUM)

Switch the clock division ratio

selection bits (bits 6 and 7 of CPUM)

Main routine

Start with an on-chip oscillator

An initial value is set as a ceramic oscillation mode.

When it is switched to an RC oscillation, its oscillation starts.

Select 1/1, 1/2, 1/8 or on-chip oscillator.

Wait by on-chip oscillator operation

until establishment of oscillator clock

When using a ceramic oscillation, wait until establlishment of

oscillation from oscillation starts.

When using an RC oscillation, wait time is not required

basically (time to execute the instruction to switch from an

on-chip oscillator meets the requirement).

Note: After system is released from reset, an on-chip oscillator turns active automatically and system operation

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