7547 datasheet(49/91 Pages) RENESAS

49 / 91 page

Rev.1.21

Nov 15, 2006

page 49 of 89

REJ03B0156-0121

7547 Group

A/D Converter

The functional blocks of the A/D converter are described below.

[A/D conversion register] AD

The A/D conversion register is a read-only register that stores the

result of A/D conversion. Do not read out this register during an A/

D conversion.

[A/D control register] ADCON

The A/D control register controls the A/D converter.

Bit 2 to 0 are analog input pin selection bits.

Bit 3 is the A/D conversion clock selection bit. When “0” is set to this

bit, the A/D conversion clock is f(XIN)/2 and the A/D conversion time

is 122 cycles of f(XIN). When “1” is set to this bit, the A/D conversion

clock is f(XIN) and the A/D conversion time is 61 cycles of f(XIN).

Bit 4 is the A/D conversion completion bit. The value of this bit re-

mains at “0” during A/D conversion, and changes to “1” at

completion of A/D conversion.

A/D conversion is started by setting this bit to “0”.

[Comparison voltage generator]

The comparison voltage generator divides the voltage between

AVSS and VREF by 1024, and outputs the divided voltages.

[Channel selector]

The channel selector selects one of ports P27/AN7 to P20/AN0,

and inputs the voltage to the comparator.

[Comparator and control circuit]

The comparator and control circuit compares an analog input volt-

age with the comparison voltage and stores its result into the A/D

conversion register. When A/D conversion is completed, the con-

trol circuit sets the A/D conversion completion bit and the A/D

interrupt request bit to “1”. Because the comparator is constructed

linked to a capacitor, set f(XIN) in order that the A/D conversion

clock is 250 kHz or over during A/D conversion.

s Notes on A/D converter

As for AD translation accuracy, on the following operating condi-

tions, accuracy may become low.

(1) Since the analog circuit inside a microcomputer becomes sen-

sitive to noise when VREF voltage is set up lower than Vcc

voltage, accuracy may become low rather than the case

where VREF voltage and Vcc voltage are set up to the same

value..

(2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the

low temperature may become extremely low compared with

that at room temperature. When the system would be used at

low temperature, the use at VREF=3.0 V or more is recom-

mended.

Fig. 58 Structure of A/D control register

Fig. 59 Structure of A/D conversion register

Read 8-bit (Read only address 003516)

(Address 003516)

Read 10-bit (read in order address 003616, 003516)

(Address 003616)

(Address 003516)

Note: High-order 6-bit of address 003616 returns “0” when read.

Not used (returns “0” when read)

A/D conversion completion bit

0 : Conversion in progress

1 : Conversion completed

Analog input pin selection bits

000 : P20/AN0

001 : P21/AN1

010 : P22/AN2

011 : P23/AN3

100 : P24/AN4

101 : P25/AN5

110 : P26/AN6

111 : P27/AN7

Notes 1: A/D conversion clock=f(XIN) can be used only

when ceramic oscillation or on-chip oscillator is used.

Select f(XIN)/2 when RC oscillation is used.

A/D control register

(ADCON : address 003416, initial value: 1016)

A/D conversion clock selection bit (Note 1)

0 : f(XIN)/2

1 : f(XIN)

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