7547 datasheet(83/91 Pages) RENESAS

83 / 91 page

Rev.1.21

Nov 15, 2006

page 83 of 89

REJ03B0156-0121

7547 Group

3. Interrupt discrimination bit

Use an LDM instruction to clear to “0” an interrupt discrimination

bit.

LDM #%0000XXXX, $0B

Set the following values to “X”

“0”: an interrupt discrimination bit to clear

“1”: other interrupt discrimination bits

Ex.) When a key-on wakeup interrupt discrimination bit is cleared;

LDM #%00001110 and $0B.

4. Interrupt discrimination bit and interrupt request bit

For key-on wakeup, UART1 bus collision detection, A/D conver-

sion and Timer 1 interrupt, even if each interrupt valid bit (interrupt

source set register (address 0A16)) is set “0: Invalid”, each inter-

rupt discrimination bit (interrupt source discrimination register

(address 0B16)) is set to “1: interrupt occurs” when corresponding

interrupt request occurs.

But corresponding interrupt request bit (interrupt request registers

1, 2 (addresses 3C16, 3D16) is not affected.

Notes on Timers

1. When n (0 to 255) is written to a timer latch, the frequency divi-

sion ratio is 1/(n+1).

2. When a count source of timer X, timer A or timer B is switched,

stop a count of the timer.

Notes on Timer X

1. CNTR0 interrupt active edge selection

CNTR0 interrupt active edge depends on the CNTR0 active edge

switch bit (bit 2 of timer X mode register (address 2B16)).

When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at

the falling edge of CNTR0 pin input signal. When this bit is “1”, the

CNTR0 interrupt request bit is set to “1” at the rising edge of

CNTR0 pin input signal.

2. Timer X count source selection

The f(XIN) (frequency not divided) can be selected by the timer X

count source selection bits (bits 1 and 0 of timer count source set

on-chip oscillator is selected.

Do not select it for the timer X count source at the RC oscillation.

3. Pulse output mode

Set the direction register of port P14, which is also used as CNTR0

pin, to output.

When the TXOUT pin is used, set the direction register of port P03,

which is also used as TXOUT pin, to output.

4. Pulse width measurement mode

Set the direction register of port P14, which is also used as CNTR0

pin, to input.

Notes on Timer A, B

1. Setting of timer value

When “1: Write to only latch” is set to the timer A (B) write control

bit (bit 0 (bit 2) of timer X mode register (address 1D16)), written

data to timer register is set to only latch even if timer is stopped or

operating. Accordingly, in order to set the initial value for timer

when it is stopped, set “0: Write to latch and timer simultaneously”

to timer A (B) write control bit.

2. Read/write of timer A

Stop timer A to read/write its data in the following state;

XIN oscillation selected by clock division ratio selection bits (bits 7

and 6 of CPU mode register (address 3B16)), and the on-chip os-

cillator output is selected as the timer A count source.

3. Read/write of timer B

Stop timer B to read/write its data in the following state;

XIN oscillation selected by clock division ratio selection bits, the

timer A underflow is selected as the timer B count source, and the

on-chip oscillator output is selected as the timer A count source.

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