7547 datasheet(46/91 Pages) RENESAS

46 / 91 page

7547 Group

Rev.1.21

Nov 15, 2006

page 46 of 89

REJ03B0156-0121

Fig. 55 Block diagram of UART serial I/O2

(2) Asynchronous Serial I/O2 (UART) Mode

Clock asynchronous serial I/O mode (UART) can be selected by

clearing the serial I/O2 mode selection bit of the serial I/O2 control

Eight serial data transfer formats can be selected, and the transfer

formats used by a transmitter and receiver must be identical.

The transmit and receive shift registers each have a buffer, but the

two buffers have the same address in memory. Since the shift reg-

ister cannot be written to or read from directly, transmit data is

written to the transmit buffer register, and receive data is read

from the receive buffer register.

The transmit buffer register can also hold the next data to be

transmitted, and the receive buffer register can hold a character

while the next character is being received.

Fig. 56 Operation of UART serial I/O2 function

XIN

1/4

PE FE

1/16

Data bus

Receive buffer register 2

Address 002E16

Receive shift register 2

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Baud rate generator 2

Frequency division ratio 1/(n+1)

Address 003216

ST/SP/PA generator

Transmit buffer register 2

Data bus

Transmit shift register 2

Address 002E16

Transmit shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

Address 002F16

ST detector

SP detector

UART2 control register

Address 003116

Character length selection bit

Address 003016

BRG count source selection bit

Transmit interrupt source selection bit

Serial I/O2 synchronous clock selection bit

Clock control circuit

Character length selection bit

7 bits

8 bits

Serial I/O2 control register

P06/SCLK2

Serial I/O2 status register

P04/RXD2

P05/TXD2

TSC=0

TBE=1

RBF=0

TBE=0

RBF=1

TBE=1

TSC=1

Transmit or receive clock

Transmit buffer 2

write signal

Generated at 2nd bit in 2-stop-bit mode

1 start bit

7 or 8 data bit

1 or 0 parity bit

1 or 2 stop bit (s)

1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).

2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit

interrupt source selection bit (TIC) of the serial I/O2 control register.

3: The receive interrupt (RI) is set when the RBF flag becomes “1.”

4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.

Notes

✽

Serial output TXD2

Serial input RXD2

Receive buffer 2

read signal

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