7547 datasheet(82/91 Pages) RENESAS

82 / 91 page

7547 Group

Rev.1.21

Nov 15, 2006

page 82 of 89

REJ03B0156-0121

5. Direction register

The values of the port direction registers cannot be read.

That is, it is impossible to use the LDA instruction, memory opera-

tion instruction when the T flag is “1”, addressing mode using

direction register values as qualifiers, and bit test instructions such

as BBC and BBS.

It is also impossible to use bit operation instructions such as CLB

and SEB and read-modify-write instructions of direction registers

for calculations such as ROR.

For setting direction registers, use the LDM instruction, STA in-

struction, etc.

Termination of Unused Pins

1. Terminate unused pins

Perform the following wiring at the shortest possible distance (20

mm or less) from microcomputer pins.

(1) I/O ports

Set the I/O ports for the input mode and connect each pin to VCC

or VSS through each resistor of 1 k

Ω to 10 kΩ. The port which can

select a built-in pull-up resistor can also use the built-in pull-up re-

sistor.

When using the I/O ports as the output mode, open them at “L” or

“H”.

• When opening them in the output mode, the input mode of the

initial status remains until the mode of the ports is switched over

to the output mode by the program after reset. Thus, the poten-

tial at these pins is undefined and the power source current may

increase in the input mode. With regard to an effects on the sys-

tem, thoroughly perform system evaluation on the user side.

• Since the direction register setup may be changed because of a

program runaway or noise, set direction registers by program

periodically to increase the reliability of program.

2. Termination remarks

(1) I/O ports setting as input mode

[1] Do not open in the input mode.

• The power source current may increase depending on the first-

stage circuit.

• An effect due to noise may be easily produced as compared with

proper termination (1) shown on the above “1. Terminate unused

pins”.

[2] Do not connect to VCC or VSS directly.

If the direction register setup changes for the output mode be-

cause of a program runaway or noise, a short circuit may occur.

[3] Do not connect multiple ports in a lump to VCC or VSS through

a resistor.

If the direction register setup changes for the output mode be-

cause of a program runaway or noise, a short circuit may occur

between ports.

Notes on Interrupts

1. Change of relevant register settings

When not requiring for the interrupt occurrence synchronous with

the following case, take the sequence shown in Figure 5.

• When switching external interrupt active edge

• When switching interrupt sources of an interrupt vector address

where two or more interrupt sources are allocated

Fig. 5 Sequence of changing relevant register

When setting the followings, the interrupt request bit of the corre-

sponding interrupt may be set to “1”.

• When switching external interrupt active edge

INT0 interrupt edge selection bit

(bit 0 of Interrupt edge selection register (address 3A16))

INT1 interrupt edge selection bit

(bit 1 of Interrupt edge selection register)

CNTR0 active edge switch bit

(bit 2 of timer X mode register (address 2B16))

Capture 0 interrupt edge selection bit

(bits 1 and 0 of capture mode register (address 2016))

Capture 1 interrupt edge selection bit

(bits 3 and 2 of capture mode register)

2. Check of interrupt request bit

When executing the BBC or BBS instruction to determine an in-

terrupt request bit immediately after this bit is set to “0”, take the

following sequence.

If the BBC or BBS instruction is executed immediately after an in-

terrupt request bit is cleared to “0”, the value of the interrupt

request bit before being cleared to “0” is read.

Set the corresponding interrupt enable bit to “0” (disabled) .

↓

Set the interrupt edge selection bit, active edge switch bit, or

the interrupt source selection bit.

↓

NOP (One or more instructions)

↓

Set the corresponding interrupt request bit to “0”

(no interrupt request issued).

↓

Set the corresponding interrupt enable bit to “1” (enabled).

Set the interrupt request bit to “0” (no interrupt issued)

↓

NOP (one or more instructions)

↓

Execute the BBC or BBS instruction

Fig. 6 Sequence of check of interrupt request bit

7547 датащи(PDF) 82 Page - Renesas Technology Corp

7547 датащи(HTML) 82 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

датащи скачать

ссылки URL