7547 datasheet(59/91 Pages) RENESAS

59 / 91 page

Rev.1.21

Nov 15, 2006

page 59 of 89

REJ03B0156-0121

7547 Group

Fig. 75 State transition

STP mode

f(XIN) oscillation: stop

On-chip oscillator: stop

WAIT mode 1

WAIT mode 2

WAIT mode 3

WAIT mode 3’

Operation clock source: On-chip oscillator (Note 2)

Operation clock source: f(XIN) (Note 1)

Notes on switch of clock

(1) In operation clock = f(XIN), the following can be selected for the CPU clock division ratio.

f(XIN)/2 (high-speed mode)

f(XIN)/8 (middle-speed mode)

f(XIN) (double-speed mode, only at a ceramic oscillation)

(2) In operation clock = On-chip oscillator, the following can be selected for the CPU clock division ratio.

ROSC/1 (On-chip oscillator double-speed mode)

ROSC/2 (On-chip oscillator high-speed mode)

ROSC/8 (On-chip oscillator middle-speed mode)

ROSC/128 (On-chip oscillator low-speed mode)

(3) After system is released from reset, and state transition of state 2

→ state 3 and state transition of state 2’ → state 3’,

ROSC/8 (On-chip oscillator middle-speed mode) is selected for CPU clock.

(4) Executing the state transition state 3 to 2 or state 3’ to 2’ after stabilizing XIN oscillation.

(5) When the state 2

→ state 3 → state 4 is performed, execute the NOP instruction as shown below

according to the division ratio of CPU clock.

1. CPUM76 = 102 (state 2

→ state 3)

2. NOP instruction

Transition from Double-speed mode: NOP ✕ 3

Transition from High-speed mode: NOP ✕ 1

Transition from Middle-speed mode: NOP ✕ 0

3. CPU4 = 12 (state 3

→ state 4)

(6) When the state 3

→ state 2 → state 1 is performed, execute the NOP instruction as shown below

according to the division ratio of CPU clock.

1. CPUM76 = 002 or 012 or 112 (state 3

→ state 2)

2. NOP instruction

Transition from On-chip oscillator double-speed mode: NOP ✕ 4

Transition from On-chip oscillator high-speed mode: NOP ✕ 2

Transition from On-chip oscillator middle-speed mode: NOP ✕ 0

Transition from On-chip oscillator low-speed mode: NOP ✕ 0

3. CPUM3 = 12 (state 2

→ state 1)

WAIT mode 4

State 4

RESET state

f(XIN) oscillation: enabled

On-chip oscillator: enabled

State 3

State 3’

WAIT mode 2’

State 2’

State 2

State 1

Interrupt

STP

instruction

Interrupt

WIT

instruction

Interrupt

CPUM3=02

CPUM3=12

CPUM76=102

(Note 3)

CPUM76=002

012

112

(Note 4)

CPUM76=102

(Note 3)

CPUM76=002

012

112

MISRG1=12

MISRG1=02

MISRG1=12

(Note 4)

MISRG1=02

Reset

released

(Note 3)

CPUM4=02

CPUM4=12

Interrupt

WIT

instruction

WIT

instruction

Interrupt

WIT

instruction

Interrupt

WIT

instruction

Interrupt

WIT

instruction

STP

instruction

STP

instruction

STP

instruction

Interrupt

f(XIN) oscillation: enabled

On-chip oscillator: stop

f(XIN) oscillation: enabled

On-chip oscillator: enabled

f(XIN) oscillation: enabled

On-chip oscillator: enabled

f(XIN) oscillation: enabled

On-chip oscillator: enabled

f(XIN) oscillation: enabled

On-chip oscillator: enabled

Oscillation stop detection circuit valid

f(XIN) oscillation: stop

On-chip oscillator: enabled

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