7547 datasheet(80/91 Pages) RENESAS

80 / 91 page

7547 Group

Rev.1.21

Nov 15, 2006

page 80 of 89

REJ03B0156-0121

APPENDIX

NOTES ON PROGRAMMING

1. Processor Status Register

(1) Initializing of processor status register

Flags which affect program execution must be initialized after a re-

set.

In particular, it is essential to initialize the T and D flags because

they have an important effect on calculations.

After a reset, the contents of the processor status register (PS) are

undefined except for the I flag which is “1”.

Reset

↓

Initializing of flags

↓

Main program

Fig. 3 Stack memory contents after PHP instruction execution

2. Decimal calculations

(1) Execution of decimal calculations

The ADC and SBC are the only instructions which will yield proper

decimal notation, set the decimal mode flag (D) to “1” with the

SED instruction. After executing the ADC or SBC instruction, ex-

ecute another instruction before executing the SEC, CLC, or CLD

instruction.

PLP instruction execution

Fig. 1 Initialization of processor status register

(2) How to reference the processor status register

To reference the contents of the processor status register (PS), ex-

ecute the PHP instruction once then read the contents of (S+1). If

necessary, execute the PLP instruction to return the PS to its origi-

nal status.

Fig. 2 Sequence of PLP instruction execution

(S)

(S)+1

Stored PS

3. JMP instruction

When using the JMP instruction in indirect addressing mode, do

not specify the last address on a page as an indirect address.

4. Multiplication and Division Instructions

(1) The index X mode (T) and the decimal mode (D) flags do not

affect the MUL and DIV instruction.

(2) The execution of these instructions does not change the con-

tents of the processor status register.

5. Read-modify-write instruction

Do not execute a read-modify-write instruction to the read invalid

address (SFR).

The read-modify-write instruction operates in the following se-

quence: read one-byte of data from memory, modify the data,

write the data back to original memory. The following instructions

are classified as the read-modify-write instructions in the 740

Family.

(1) Bit management instructions: CLB, SEB

(2) Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF

(3) Add and subtract instructions: DEC, INC

(4) Logical operation instructions (1’s complement): COM

Add and subtract/logical operation instructions (ADC, SBC, AND,

EOR, and ORA) when T flag = “1” operate in the way as the read-

modify-write instruction. Do not execute the read invalid SFR.

When the read-modify-write instruction is executed to read invalid

SFR, the instruction may cause the following consequence: the in-

struction reads unspecified data from the area due to the read

invalid condition. Then the instruction modifies this unspecified

data and writes the data to the area. The result will be random

data written to the area or some unexpected event.

Set D flag to “1”

↓

ADC or SBC instruction

↓

NOP instruction

↓

SEC, CLC, or CLD instruction

Fig. 4 Status flag at decimal calculations

(2) Notes on status flag in decimal mode

When decimal mode is selected, the values of three of the flags in

the status register (the N, V, and Z flags) are invalid after a ADC or

SBC instruction is executed.

The carry flag (C) is set to “1” if a carry is generated as a result of

the calculation, or is cleared to “0” if a borrow is generated. To de-

termine whether a calculation has generated a carry, the C flag

must be initialized to “0” before each calculation. To check for a

borrow, the C flag must be initialized to “1” before each calcula-

tion.

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