38D2 datasheet(28/136 Pages) RENESAS

28 / 136 page

Rev.3.02

Apr 10, 2008

Page 28 of 131

REJ03B0177-0302

38D2 Group

<Notes>

The interrupt request bit may be set to “1” in the following cases.

• When setting the external interrupt active edge

Related bits: INT0 interrupt edge selection bit

(bit 0 of interrupt edge selection register

(address 003A16))

INT1 interrupt edge selection bit

(bit 1 of interrupt edge selection register)

INT2 interrupt edge selection bit

(bit 2 of interrupt edge selection register)

CNTR0 activate edge switch bit

(bits 6 and 7 of timer X control register 1

(address 002E16))

CNTR1 activate edge switch bit

(bits 6 of timer Y mode register

(address 003816))

• When switching the interrupt sources of an interrupt vector

address where two or more interrupt sources are assigned

Related bit:

Timer Y/CNTR1 interrupt switch bit

(bit 3 of interrupt edge selection register)

If it is not necessary to generate an interrupt synchronized with

these settings, take the following sequence.

(1) Set the corresponding enable bit to “0” (disabled).

(2) Set the interrupt edge selection bit (the active edge switch

bit) or the interrupt source bit.

(3) Set the corresponding interrupt request bit to “0” after one

or more instructions have been executed.

(4) Set the corresponding interrupt enable bit to “1” (enabled).

Fig. 20 Timing of interrupt request generation, interrupt request bit, and interrupt acceptance

(1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1.

(2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2.

The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt

requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2

separately.

T1 T2 T3 : Interrupt acceptance timing points

IR1 IR2 : Timings points at which the interrupt request bit is set to “1”.

Note : Period 2 indicates the last

φ cycle during one instruction cycle.

IR1T2

SYNC

IR2 T3

Internal clock

Instruction cycle

Push onto stack

Vector fetch

Instruction cycle

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