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38D2 датащи(PDF) 22 Page - Renesas Technology Corp |
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38D2 датащи(HTML) 22 Page - Renesas Technology Corp |
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22 / 136 page ![]() Rev.3.02 Apr 10, 2008 Page 22 of 131 REJ03B0177-0302 38D2 Group Fig. 15 Port block diagram (3) (20) COM0-COM3 VL3 VL2 VL1 VSS Gate input signal of each gate depends on the duty ratio and bias values. (17) Port P57 Serial I/O ready output Data bus Port latch Serial I/O mode selection bit Serial I/O enable bit SRDY1 output enable bit Direction register Pull-up control Key-on wakeup interrupt input Key input control (19) Port P62 Data bus Port latch Direction register Xc oscillation enabled + Pull-up control Xc oscillation enabled Port P61 Oscillator Xc oscillation enabled (18) Port P61 Data bus Port latch Direction register Xc oscillation enabled Sub-clock generation circuit input Xc oscillation enabled + Pull-up control (16) Port P56 Serial I/O synchronous clock selection bit Data bus Serial I/O clock output Serial I/O mode selection bit Serial I/O enable bit Port latch Direction register Serial I/O enable bit Pull-up control Serial I/O clock input Key-on wakeup interrupt input Key input control (15) Port P55 Data bus Serial I/O enable bit Transmit enable bit Serial I/O output P55/TxD1 P-channel output disable bit Port latch Direction register Pull-up control Key-on wakeup interrupt input Key input control |
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