38D2 datasheet(36/136 Pages) RENESAS

36 / 136 page

Rev.3.02

Apr 10, 2008

Page 36 of 131

REJ03B0177-0302

38D2 Group

Fig. 27 Waveform of PWM/IGBT

(1) Write Order to Timer X

• In the timer mode, pulse output mode, event counter mode and

pulse width measurement mode, write to the following

registers in the order as shown below;

the timer X register (extension),

the timer X register (low-order),

the timer X register (high-order).

Do not write to only one of them.

When the above mode is set and timer X operates as the 16-bit

counter, if the timer X register (extension) is never set after

reset is released, setting the timer X register (extension) is not

required. In this case, write the timer X register (low-order)

first and the timer X register (high-order). However, once

writing to the timer X register (extension) is executed, note that

the value is retained to the reload latch.

• Write to the timer X register by the 16-bit unit. Do not read the

timer X register while write operation is performed. If the

write operation is not completed, normal operation will not be

performed.

• In the IGBT output and PWM modes, do not write “1” to the

timer X register (extension). Also, when “1” is already written

to the timer X register, be sure to write “0” to the register

before using.

Write to the following registers in the order as shown below;

the compare registers 1, 2, 3 (high- and low-order),

the timer X register (extension),

the timer X register (low-order),

the timer X register (high-order).

It is possible to use whichever order to write to the compare

registers 1, 2, 3 (high- and low-order). However, write both the

compare registers 1, 2, 3 and the timer X register at the same

time.

For the compare registers, set a value less than the setting value

in the timer X register. Also, do not set “0016”.

(2) Read Order to Timer X

• In all modes, read the following registers in the order as shown

below;

the timer X register (extension),

the timer X register (high-order),

the timer X register (low-order).

When reading the timer X register (extension) is not required,

read the timer X register (high-order) first and the timer X

Read order to the compare registers 1, 2, 3 is not specified.

• Read from the timer X register by the 16-bit unit. Do not write

to the timer X register while read operation is performed. If the

read operation is not completed, normal operation will not be

performed.

(3) Write to Timer X

• Which write control can be selected by the timer X write

control bit (b3) of the timer X mode register (address 2D16),

writing data to both the latch and the timer at the same time or

writing data only to the latch. When writing a value to the

timer X address to write to the latch only, the value is set into

the reload latch and the timer is updated at the next underflow.

After reset release, when writing a value to the timer X

address, the value is set into the timer and the timer latch at the

same time, because they are written at the same time.

When writing to the latch only, if the write timing to the high-

order reload latch and the underflow timing are almost the

same, the value is set into the timer and the timer latch at the

same time. In this time, counting is stopped during writing to

the high-order reload latch.

• Switch the frequency division or count source* while the timer

count is stopped.

*This also applies when the frequency divider output is selected

as the timer count source and the count source is switched in

conjunction with a transition between operating modes (on-

chip oscillator mode, XIN mode, or low-speed mode). Be

careful when changing settings in the CPU mode register.

Timer X count source

Timer X PWM mode

IGBT output mode

× ts

(n+1)

× ts

The following PWM waveform is output;

Duty of TXOUT1 output :{(n+1)-m}/(n+1),

Duty of TXOUT2 output :(p-q)/(n+1),

Period :(n+1)

× ts

TXOUT1 output

(TXCON1 bit 5 = “0”)

TXOUT2 output

(TXCON2 bit 1 = “0”)

× ts

n : Timer X setting value

m: Compare register 1 setting value

p : Compare register 2 setting value

q : Compare register 3 setting value

ts: One period of timer X count source

External trigger (INT0 source)

is generated.

INT1 or INT2 source is generated.

Level is forcibly “L” only IGBT

output mode.

Level is “H” only IGBT

output mode.

38D2 датащи(PDF) 36 Page - Renesas Technology Corp

38D2 датащи(HTML) 36 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL