38D2 datasheet(14/136 Pages) RENESAS

14 / 136 page

Rev.3.02

Apr 10, 2008

Page 14 of 131

REJ03B0177-0302

38D2 Group

[CPU Mode Register (CPUM)] 003B16

The CPU mode register contains the stack page selection bit, etc.

This register is allocated at address 003B16.

After the system is released from reset, the mode depends on the

OSCSEL pin state in the QzROM version.

When the OSCSEL pin state is GND level, only the on-chip

oscillator starts oscillation. The XIN-XOUT oscillation stops

oscillating, and XCIN and XCOUT pins function as I/O ports. The

operating mode is the on-chip oscillator mode.

When the OSCSEL pin state is Vcc level, the XIN-XOUT

oscillation divided by 8 starts oscillation. The on-chip oscillator

stops oscillating, and the XCIN and XCOUT pins function as I/O

ports. The operating mode is the frequency/8 mode.

In the flash memory version, only the on-chip oscillator starts

oscillating. The XIN-XOUT oscillation stops oscillating, and the

XCIN and XCOUT pins function as I/O ports. The operating mode

is the on-chip oscillator mode.

When the main clock or sub-clock is used, after the XIN-XOUT

oscillation and the XCIN-XCOUT oscillation are enabled, wait in

the on-chip oscillator mode etc. until the oscillation stabilizes,

and then switch the operation mode.

When the main clock is not used (XIN-XOUT oscillation and an

external clock input are not used), connect the XIN pin to VCC

through a resistor and leave XOUT open.

[CPU Mode Register 2 (CPUM2)] 001116

The CPU mode register 2 contains the control bits for the on-chip

oscillator.

The CPU mode register 2 is allocated at address 001116.

Fig. 7 Structure of CPU mode register

On-chip oscillator stop bit

0 : Oscillating

1 : Stopped

Not used (do not write “1”)

Not used (returns “0” when read)

Not used (do not write “1”)

Processor mode bits

b1 b0

0 0 : Single-chip mode

0 1 :

1 0 :

1 1 :

Stack page selection bit

0 : 0 page

1 : 1 page

Internal system clock selection bit

0 : Main clock selected (includes OCO, XIN)

1 : XCIN–XCOUT selected

Port Xc switch bit

0 : I/O port function (Oscillation stop)

1 : XCIN–XCOUT oscillating function

XIN–XOUT oscillation stop bit

0 : Oscillating

1 : Stopped

Main clock division ratio selection bit (Valid only when CM3=0)

b7 b6

0 0 : f(XIN)/2 (frequency/2 mode)

0 1 : f(XIN)/8 (frequency/8 mode)

1 0 : f(XIN)/4 (frequency/4 mode)

1 1 : On-chip oscillator

CPU mode register 2

CPUM2

(address 001116, QzROM version, OSCSEL=L, initial value: 0016)

(

QzROM version, OSCSEL=H, initial value: 0116)

(

Flash memory version,

initial value: 0016)

CM8

CPU mode register

CPUM

(address 003B16, QzROM version, OSCSEL=L, initial value: E016)

(

QzROM version, OSCSEL=H, initial value: 4016)

(

Flash memory version,

initial value: E016)

CM0

CM1

CM2

CM3

CM4

CM5

CM6

CM7

Not available

Notes 1: When the on-chip oscillator is selected by the watchdog timer count source selection bit 2 (bit 5 of

watchdog timer control register (address 002916)), the on-chip oscillator does not stop

even when the on-chip oscillator stop bit is set to “1”.

Also, when the low-speed mode is set, the on-chip oscillator stops regardless of the value of this bit in

the QzROM version. The on-chip oscillator does not stop in the flash memory version, so set this bit to

“1” to stop the oscillation.

In on-chip oscillator mode, even if this bit is set to “1”, the on-chip oscillator does not stop in the flash

memory version, but stops in the QzROM version.

2: In low-speed mode, the XCIN-XCOUT oscillation stops if the port XC switch bit is set to “0”.

3: In XIN mode, the XIN-XOUT oscillation does not stop even if the XIN-XOUT oscillation stop bit is set to “1”.

4: 12.5 MHz < f(XIN)

≤ 16 MHz is not available in the frequency/2 mode.

(1)

(4)

(2)

(3)

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