38D2 datasheet(27/136 Pages) RENESAS

27 / 136 page

Rev.3.02

Apr 10, 2008

Page 27 of 131

REJ03B0177-0302

38D2 Group

• Interrupt Request Generation, Acceptance, and

Handling

Interrupts have the following three phases.

(i) Interrupt Request Generation

An interrupt request is generated by an interrupt source

(external interrupt signal input, timer underflow, etc.) and

the corresponding request bit is set to “1”.

(ii) Interrupt Request Acceptance

Based on the interrupt acceptance timing in each instruction

cycle, the interrupt control circuit determines acceptance

conditions (interrupt request bit, interrupt enable bit, and

interrupt disable flag) and interrupt priority levels for

accepting interrupt requests. When two or more interrupt

requests are generated simultaneously, the highest priority

interrupt is accepted. The value of interrupt request bit for

an unaccepted interrupt remains the same and acceptance is

determined at the next interrupt acceptance timing point.

(iii) Handling of Accepted Interrupt Request

The accepted interrupt request is processed.

Figure 18 shows the time up to execution in the interrupt routine,

and Figure 19 shows the interrupt sequence.

Figure 20 shows the timing of interrupt request generation,

interrupt request bit, and interrupt request acceptance.

• Interrupt Handling Execution

When interrupt handling is executed, the following operations

are performed automatically.

(1) Once the currently executing instruction is completed, an

interrupt request is accepted.

(2) The contents of the program counters and the processor

status register at this point are pushed onto the stack area in

order from 1 to 3.

1. High-order bits of program counter (PCH)

2. Low-order bits of program counter (PCL)

3. Processor status register (PS)

(3) Concurrently with the push operation, the jump address of

the corresponding interrupt (the start address of the interrupt

processing routine) is transferred from the interrupt vector to

the program counter.

(4) The interrupt request bit for the corresponding interrupt is

set to “0”. Also, the interrupt disable flag is set to “1” and

multiple interrupts are disabled.

(5) The interrupt routine is executed.

(6) When the RTI instruction is executed, the contents of the

registers pushed onto the stack area are popped off in the

order from 3 to 1. Then, the routine that was before running

interrupt processing resumes.

As described above, it is necessary to set the stack pointer and

the jump address in the vector area corresponding to each

interrupt to execute the interrupt processing routine.

Fig. 18 Time up to execution in interrupt routine

Fig. 19 Interrupt sequence

7 cycles

Interrupt request

generated

Interrupt request

acceptance

Interrupt routine

starts

Interrupt sequence

0 to 16 cycles

7 to 23 cycles

* When executing DIV instruction

Main routine

Stack push and

Vector fetch

Interrupt handling

routine

SYNC

Push onto stack

Vector fetch

Address bus

Data bus

Execute interrupt

routine

S,SPS

S-1,SPS S-2,SPS

AL,AH

Not used

PCH

PCL

SYNC : CPU operation code fetch cycle

(This is an internal signal that cannot be observed from the external unit.)

BL, BH: Vector address of each interrupt

AL, AH: Jump destination address of each interrupt

SPS

: “0016” or “0116”

([SPS] is a page selected by the stack page selection bit of CPU mode register.)

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