38D2 datasheet(46/136 Pages) RENESAS

46 / 136 page

Rev.3.02

Apr 10, 2008

Page 46 of 131

REJ03B0177-0302

38D2 Group

LCD DRIVE CONTROL CIRCUIT

The 38D2 Group has the built-in Liquid Crystal Display (LCD)

drive control circuit consisting of the following.

• LCD display RAM

• Segment output disable register

• LCD mode register

• Selector

• Timing controller

• Common driver

• Segment driver

• Bias control circuit

A maximum of 24 segment output pins and 4 common output

pins can be used.

Up to 96 pixels can be controlled for an LCD display. When the

LCD enable bit is set to “1” after data is set in the LCD mode

RAM, the LCD drive control circuit starts reading the display

data automatically, performs the bias control and the duty ratio

control, and displays the data on the LCD panel.

Fig. 38 Structure of LCD related registers

Table 11

Maximum number of display pixels at each duty ratio

Duty ratio

Maximum number of display pixels

48 dots

or 8 segment LCD 6 digits

72 dots

or 8 segment LCD 9 digits

96 dots

or 8 segment LCD 12 digits

LCD mode register

(LM : address 001316)

Duty ratio selection bits

b1b0

0 0 : Not used

0 1 : 2 (use COM0, COM1)

1 0 : 3 (use COM0-COM2)

1 1 : 4 (use COM0-COM3)

Bias control bit

0 : 1/3 bias

1 : 1/2 bias

LCD enable bit

0 : LCD OFF

1 : LCD ON

LCD drive timing selection bit

0 : Type A

1 : Type B

LCD circuit divider division ratio selection bits

b6b5

0 0 : Clock input

0 1 : 2 division of clock input

1 0 : 4 division of clock input

1 1 : 8 division of clock input

LCDCK count source selection bit (Note 3)

0 : f(XCIN)/32

1 :

φSOURCE/8192

Segment output disable register 0

(SEG0 : address 0FF416)

Segment output disable bit 0

0 : Segment output SEG0

1 : Output port P00

Segment output disable bit 1

0 : Segment output SEG1

1 : Output port P01

Segment output disable bit 2

0 : Segment output SEG2

1 : Output port P02

Segment output disable bit 3

0 : Segment output SEG3

1 : Output port P03

Segment output disable bit 4

0 : Segment output SEG4

1 : Output port P04

Segment output disable bit 5

0 : Segment output SEG5

1 : Output port P05

Segment output disable bit 6

0 : Segment output SEG6

1 : Output port P06

Segment output disable bit 7

0 : Segment output SEG7

1 : Output port P07

Segment output disable register 1

(SEG1 : address 0FF516)

Segment output disable bit 8

0 : Segment output SEG8

1 : Output port P10

Segment output disable bit 9

0 : Segment output SEG9

1 : Output port P11

Segment output disable bit 10

0 : Segment output SEG10

1 : Output port P12

Segment output disable bit 11

0 : Segment output SEG11

1 : Output port P13

Segment output disable bit 12

0 : Segment output SEG12

1 : Output port P14

Segment output disable bit 13

0 : Segment output SEG13

1 : Output port P15

Segment output disable bit 14

0 : Segment output SEG14

1 : Output port P16

Segment output disable bit 15

0 : Segment output SEG15

1 : Output port P17

Segment output disable register 2

(SEG2 : address 0FE616)

Segment output disable bit 16

0 : Segment output SEG16

1 : Output port P20

Segment output disable bit 17

0 : Segment output SEG17

1 : Output port P21

Segment output disable bit 18

0 : Segment output SEG18

1 : Output port P22

Segment output disable bit 19

0 : Segment output SEG19

1 : Output port P23

Segment output disable bit 20

0 : Segment output SEG20

1 : Output port P24

Segment output disable bit 21

0 : Segment output SEG21

1 : Output port P25

Segment output disable bit 22

0 : Segment output SEG22

1 : Output port P26

Segment output disable bit 23

0 : Segment output SEG23

1 : Output port P27

Notes 1: Only pins set to output ports by the direction register can be controlled to switch to output ports or segment outputs by the segment output disable

2: When the VL pin input selection bit (VLSEL) of the LCD power control register (address 003816) is “1”, settings of the segment output disable bit 22 and

segment output disable bit 23 are invalid.

3: LCDCK is a clock for an LCD timing controller.

φ SOURCE represents the supply source of internal clock φ.

XIN input: in the frequency/2, 4 or 8 mode, Internal on-chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-speed mode.

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