38D2 datasheet(39/136 Pages) RENESAS

39 / 136 page

Rev.3.02

Apr 10, 2008

Page 39 of 131

REJ03B0177-0302

38D2 Group

• CNTR1 Interrupt Active Edge Selection

CNTR1 interrupt active edge depends on the CNTR1 active edge

switch bit. However, in pulse width HL continuously

measurement mode, CNTR1 interrupt request is generated at

both rising and falling edges of CNTR1 pin input signal

regardless of the setting of CNTR1 active edge switch bit.

• Timer Y Read/Write Control

• When reading from/writing to timer Y, read from/write to both

the high-order and low-order bytes of timer Y. When the value

is read, read the high-order bytes first and the low-order bytes

next. When the value is written, write the low-order bytes first

and the highorder bytes next.

Write to or read from the timer X register in 16-bit units. If

reading from the timer Y register during write operation or

writing to it during read operation is performed, normal

operation will not be performed.

• Which write control can be selected by the timer Y write

control bit (b0) of the timer Y control register (address

003916), writing data to both the latch and the timer at the

same time or writing data only to the latch. When writing a

value to the timer Y address to write to the latch only, the

value is set into the reload latch and the timer is updated at the

next underflow. After reset release, when writing a value to the

timer Y address, the value is set into the timer and the timer

latch at the same time, because they are set to write at the same

time.

When writing to the latch only, if the write timing to the high-

order reload latch and the underflow timing are almost the

same, the value is set into the timer and the timer latch at the

same time. In this time, counting is stopped during writing to

the high-order reload latch.

• This also applies when the frequency divider output is selected

as the timer count source and the count source is switched in

conjunction with a transition between operating modes (on-

chip oscillator mode, XIN mode, or low-speed mode). Be

careful when changing settings in the CPU mode register.

Fig. 30 Structure of timer Y related registers

Timer Y control register

(TYCON: address 003916)

Timer Y write control bit

0 : Write data to both timer latch and timer

1 : Write data to timer latch only

Timer Y count source selection bit

0 : Frequency divider output

1 : f(XCIN)

Timer Y frequency division selection bits

b3 b2

0 0 : 1/16

× φSOURCE

0 1 : 1/1

× φSOURCE

1 0 : 1/2

× φSOURCE

1 1 : 1/256

× φSOURCE

Not used (returns “0” when read)

φ SOURCE: represents the supply source of internal clock φ.

XIN input: in the frequency/2, 4 or 8 mode,

Internal on-chip oscillator divided by 4 in the on-chip

oscillator mode, and Sub clock in the low-speed mode.

Real time port control bits (P46, P47 )

b1 b0

0 0 : Real time port function invalid

0 1 : Do not set

1 0 : Do not set

1 1 : Real time port function valid

P46 data for real time port

P47 data for real time port

Timer Y operating mode bits

b5 b4

0 0 : Timer mode

0 1 : Period measurement mode

1 0 : Event counter mode

1 1 : Pulse width HL continuous measurement mode

CNTR1 active edge switch bit

0 : Count at rising edge in event counter mode

Measure falling period in period measurement mode

Falling edge active for CNTR1 interrupt

1 : Count at falling edge in event counter mode

Measure rising period in period measurement mode

Rising edge active for CNTR1 interrupt

Timer Y count stop bit

0 : Count operation

1 : Count stop

Timer Y mode register

(TYM: address 003816)

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