ORSPI4 datasheet(167/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

167

30919A

30A19B

[0:7]

RX_DPRAM_1_FIFO

_URRUN_STS

Underrun status of bank 1 DPRAM FIFOs 0 to 7. These are enabled by

RX_DPRAM_FIFO_URRUN_INT_EN[1] (register 30912[A], 30A12[B]).

These bits clear when read, but will set immediately if the condition persists.

3091A A

30A1A B

[0:7]

RX_DPRAM_2_FIFO

_URRUN_STS

Underrun status of bank 2 DPRAM FIFOs 0 to 7. These are enabled by

RX_DPRAM_FIFO_URRUN_INT_EN[2] (register 30912[A], 30A12[B]).

These bits clear when read, but will set immediately if the condition persists.

3091B A

30A1B B

[0:7]

RX_DPRAM_3_FIFO

_URRUN_STS

Underrun status of bank 3 DPRAM FIFOs 0 to 7. These are enabled by

RX_DPRAM_FIFO_URRUN_INT_EN[3] (register 30912[A], 30A12[B]).

These bits clear when read, but will set immediately if the condition persists.

3091C A

30A1C B

[0]

RX_PLL_LOL_STS

Status ﬂag for loss of lock in PLL within the SPI4 receive core. This ﬂag is

enabled by RX_PLL_LOL_INT_EN (register 30913[A], 30A13[B]).

[1]

RX_BAS_DONE_ST

Status ﬂag for SPI4 receive core completing the baselining process. Base-

lining is the self-alignment power-up process that the macro does after it

detects lock of the PLL. This ﬂag is enabled by RX_BAS_DONE_INT_EN.

(register 30913[A], 30A13[B])

[2]

RX_BAS_ERR_STS

Status ﬂag for SPI4 receive core failing its internal self-alignment process.

This ﬂag is enables by RX_BAS_INT_EN (register 30913[A], 30A13[B]).

[3]

RX_DSKW_DONE_S

Status ﬂag for SPI4 receive dynamic alignment complete. This ﬂag is

enabled by RX_DSKW_DONE_INT_EN.

[4]

RX_DSKW_ERR_ST

Status ﬂag for SPI4 receive core failing to dynamically align. This ﬂag is

enabled by RX_DSKW_ERR_INT_EN (register 30913[A], 30A13[B]).

[5]

RX_TRN_DET_STS

Status ﬂag for SPI4 receive core detecting training patterns. This ﬂag is

enabled by RX_TRN_DET_INT_EN (register 30913[A], 30A13[B]).

[6]

RX_ALGN_OFF_ST

Status ﬂag for loss of data alignment due to excess consecutive DIP4 errors.

This ﬂag is enabled by RX_ALIGN_OFF_INT_EN (register 30913[A],

30A13[B]).

[7]

TX_STATUS_LOF_S

Status ﬂag for TX status frame having too many consecutive DIP2 errors.

This ﬂag is enabled by TX_STATUS_LOF_INT_EN (register 30913[A],

30A13[B]).

3091D A

30A1D B

[0:1]

Reserved

[2]

RX_ILLEGAL_CTL_

STS

Status ﬂag indicating that an illegal control work was received

[3:4]

Reserved

[5]

RX_DIP4_ERR_STS 00

Status ﬂag for DIP4 error

[6]

TX_DIP2_ERR_STS

Flag for error in framing TSTAT[0:1] inputs. This can be an unexpected 11

pattern or a DIP2 error.

[7]

RX_ASYNC_FIFO_O

VERRUN_STS

Status ﬂag for RX FIFO overrun inside S4RDP block.

SPI4 Core TX Status Registers (Read and Write)

30928 A

30A28 B

[0:7]

TX_DPRAM_0_FIFO

_OVERRUN_STS

Overrun status of bank 0 TX DPRAM FIFOs 0 to 7. These are enabled by

TX_DPRAM_FIFO_OVERRUN_INT_EN[0]. These bits clear when read, but

will set immediately if the condition persists. This will happen when writing to

the DPRAM FIFOs while SPI[A,B]_k_FIFO_FULL_j is high.

30929 A

30A29 B

[0:7]

TX_DPRAM_1_FIFO

_OVERRUN_STS

Overrun status of bank 1 TX DPRAM FIFOs 0 to 7. These are enabled by

TX_DPRAM_FIFO_OVERRUN_INT_EN[1]. These bits clear when read, but

will set immediately if the condition persists. This will happen when writing to

the DPRAM FIFOs while SPI[A,B]_k_FIFO_FULL_j is high.

Table 47. Memory Map (Continued)

(0x)

Abso-

lute

Address

Bit

Name

Reset

Value

(0x)

Description

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