ORSPI4 datasheet(155/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

155

ORSPI4 Memory Map

The ORSPI4 device features a variety of programming options which include all the OIF-SPI-4.2.0 speciﬁed conﬁg-

urable parameters. The base addresses for each functional block in the ORSPI4 device is shown in Figure 87 and

Table 45.

The SPIA and SPIB receive cores contain RAM blocks that are conﬁgured through writes to the address range

0x31000 - 0x317FF. Prior to conﬁguring any of these memories, the user has to select one of the memories by writ-

ing into the appropriate memory select bit in address 0x30917 (SPIA) and 0x30A17 (SPIB).

All interrupts on ORSPI4 are maskable and edge generated. Each interrupt source has a corresponding status

latch bit that can be viewed as software status register bits. At the end of a status register read, both the status and

edge-triggered interrupt register will be cleared. If the active interrupt condition still persists after the status register

read, the status register will continue to show this condition but the edge-triggered interrupt register will remain

clear not causing another interrupt.

Every interrupt or status register bit has an interrupt enable bit that must be set to ‘1’ to generate the associated

interrupt or read the status. Each interrupt enable for the DPRAMs in SPIA and SPI4 blocks controls or enables

eight interrupt sources. These enable registers are at register address 30912, 30943, (SPIA) 30A12, and 30A43

(SPIB). These 32 bits enable/disable 256 interrupts. All other interrupt enables are unique to an interrupt source.

To make the interrupt structure user-friendly, two special top-level interrupt registers are provided. Each of the bits

in these top-level interrupt registers point to speciﬁc functional blocks that caused an interrupt. The user can poll

these top-level interrupt registers to check which block has caused an interrupt and then poll the relevant lower-

level interrupts corresponding to a block. Each of the bits in the top-level interrupt status register 30B29 shown in

Table 46 point to a speciﬁc functional block in the ORSPI4 device. Each of the bits in the SPIA or SPIB DPRAM top-

level interrupt status register 30B2A is the collective OR of its associated lower-level interrupts.

Figure 87. SPI4 Core Programming Addresses in ORSPI4

FPGA

SYS_BUS

SLAVE_IF

Control & Status registers

To control SERDES

Channels

Control & Status registers

To control SPIA

Control & Status registers

To control SPIB

Global

Configuration

Memories

MEM_IF

308XX

309XX

30AXX

30BXX

CORE_IF

SPI4_IF

COMM_IF

3xxxx Hex Address

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