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ORCA ORSPI4 Data Sheet

136

FPGA/Memory Controller Core Interface Description

Table 42 lists the signals at the FPGA/Core interface for the Memory Controller block.

Table 42. FPGA/Embedded Core Signals

Memory Controller - Detailed Description

Write Data and Instruction FIFOs

The Write Data FIFO (WDFIFO) stores data written into it by logic in the FPGA. The conﬁguration is 64 by 74 bits.

Read/write pointers and ﬁll-level logic is included. The FIFOs also function as an asynchronous clock domain

boundary between the FPGA generated write clock and the Memory Controller (MC) system clock (MC_SYSCLK).

Writes from the FPGA that are asynchronous to the memory clock (K, K#) are allowed. It is also possible to run the

FIFO in synchronous mode by looping back the 1x clock via the FPGA to the FIFO write clock (MC_WCLK).

A set of 72 data signals is available across the core-FPGA interface. Of the 72, eight signals can be either used for

parity or data. The core, however, passes the data transparently to the QDRII SRAM. Data length is speciﬁed in

terms of FIFO lines. If data length is > 64 FIFO lines, then the user must segment the data.

The Write Instruction FIFO (WIFIFO) is conﬁgured 4 by 32 bits respectively, in order to store up to 4 instructions

that are written to the MC by logic in the FPGA. The instruction ﬁelds are ID (data/address coherency), data length

(number of cache lines) and address (for QDR memory). Write instruction and data word formats are shown in Fig-

ure 72.

Signal

Direction

From /To

Description

QDRII SRAM Read/Write Control

F_MC_WD[73:0]

FPGA

→ Core Write data to Memory Controller Write Data FIFO

F_MC_WI[31:0]

FPGA

→ Core Write instruction to Memory Controller Read Instruction FIFO

MC_RD[71:0]

Core

→ FPGA Read data from Memory Controller Read Data FIFO

F_MC_RI[31:0]

FPGA

→ Core Read instruction to Memory Controller Write Instruction FIFO

MC_WDFIFO_FULL

Core

→ FPGA

Full ﬂag from MC Write data FIFO. Full threshold is set by the

MC_FULL_THRESHOLD register bits.

MC_WIFIFO_FULL

Core

→ FPGA

Full ﬂag from MC Write instruction FIFO. MC_WIFIFO_FULL high indicates

that only one more instruction can be written to the instruction FIFO.

MC_RDFIFO_EMPTY

Core

→ FPGA

Empty ﬂag from MC Read data FIFO. Empty threshold is set by the

MC_EMPTY_THRESHOLD register bits.

MC_RIFIFO_FULL

Core

→ FPGA

Full ﬂag from MC Read instruction FIFO. MC_RDFIFO_FULL HIGH indicates

that only one more instruction can be written to the instruction FIFO.

F_FMC_WDFIFO_WE

FPGA

→ Core Write enable to Write Data FIFO

F_FMC_WIFIFO_WE

FPGA

→ Core Write enable to Write Instruction FIFO

F_FMC_RDFIFO_RE

FPGA

→ Core Read enable to Read data FIFO

F_FMC_RIFIFO_WE

FPGA

→ Core Write enable to Read Instruction FIFO

F_MC_WCLK

FPGA

→ Core Memory Controller Write clock

F_MC_RCLK

FPGA

→ Core Memory Controller Read clock

MC_SYSCLK

Core

→ FPGA Internal system clock for the Memory Controller i/f

F_MC_REFCLK

FPGA

→ Core Memory Controller Reference clock

FPGA_RESET_MC

FPGA

→ Core Memory Controller Asynchronous Soft Reset

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