ORSPI4 datasheet(132/263 Pages) LATTICE

132 / 263 page

Lattice Semiconductor

ORCA ORSPI4 Data Sheet

132

Figure 70. “Near End” vs. “Far End” Loopback. (NOTE: xx = A, B, C, or D)

The loopback mode can also be characterized by the physical location of the loopback connection. There are two

possible loopback modes supported by the SERDES logic:

• High-speed serial loopback at the CML buffer interface (near end)

• Parallel loopback at the SERDES boundary (far end)

These two loopback modes are described in more detail in the following sections. As noted earlier, other special-

ized loopback modes can be obtained by conﬁguration of the FPGA logic or by connections external to the FPSC.

High-Speed Serial Loopback at the CML Buffer Interface

The high-speed serial loopback mode has the serial transmit signals looped back internally to the serial receive cir-

cuitry. The internal loopback path is from the input connection to the transmit CML buffer to the output connection

from the receive CML buffer. The data are sourced on the TWDx[31:0], TCOMMAx[3:0] and TBIT9x[3:0] signal lines

and received on the MRWDx[39:0] signal lines. The serial loopback path does not include the high-speed input and

output buffers. If TESTEN_x is set, the HDOUTP_x and HDOUTN_x outputs are active in this mode while the CML

input buffers are powered down. The device is otherwise in its normal mode of operation. This mode is normally

used for tests where the data source and destination are on the same card and is the basic loopback path shown in

Table 37.

The data rate selection bits, TXHR and RXHR, in the channel conﬁguration registers must be conﬁgured to carry

the same value. Table 37 summarize the settings of the control interface register conﬁguration bits for high-speed

serial loopback.

Device Under Test (DUT)

CML

Buffer

CML

Buffer

HDIN[P:N]_xx

Non-Functional

Embedded Core

FPGA Logic

MRWDxx[39:0]

Receive

Transmit

TWDxx[31:0]

TCOMMAxx[3:0]

TBIT9xx[3:0]

HDOUT[P:N]_xx

Data

Checking

Data

Generation

Active

(to Eye Diagram

Measurement or

remote System

Card)

Test Equipment

or Logic on Local

System Card

(a) “Near End” Loopback

High Speed

Serial Loopback

Connection

Device Under Test (DUT)

Data

Generation

Data

Checking

HDIN[P:N]_xx

HDOUT[P:N]_xx

Non-Functional

Active

(to Logic on

Local System

Card)

(b) “Far End” Loopback

FPGA Logic

MRWDxx[39:0]

Receive

Transmit

TWDxx[31:0]

TCOMMAxx[3:0]

TBIT9xx[3:0]

MUX

8B/10B SERDES

CML

Buffer

8B/10B

CML

Buffer

SERDES Block

Parallel

Loopback

Connection

SERDES

Embedded Core

Test Equipment

or Logic Remote

System Card

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