ORSPI4 datasheet(137/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

137

Figure 72. Write Data and Instruction Word Formats

The user starts a write cycle by writing data to the WDFIFO. The maximum data length is 63 lines deep and the

minimum is one 72-bit data word (or one line). The user provides the instruction word associated with a data string

during the write period for the last word of the data. This sequence can continue to repeat as long as the

MC_WxFIFO_FULL ﬂags from the embedded core remain inactive. Once the MC_WIFIFO_FULL ﬂag is asserted,

the user may send data words to the WDFIFO locations (assuming the MC_WDFIFO_FULL ﬂag has not been

asserted) and write one last instruction word to the instruction FIFO as the last data word is written into the data

FIFO.

The timing diagram for the write interface for a typical write sequence is shown in Figure 73. The write sequence in

this case consists of writing 32 words to location A0 followed by one word each to locations A1, A2, A3 and A4. The

MC_WIFIFO_FULL is asserted after the instruction for location A2 has been written, indicating that only one more

instruction may be written to the instruction FIFO. The write to location A4 cannot occur until the

MC_WIFIFO_FULL ﬂag is deasserted. The MC_WDFIFO_FULL ﬂag remains low in this case since the full thresh-

old for the data FIFO has not been reached

Figure 73. ORSPI4 Memory Controller Interface to FPGA — Write Timing Diagram

In the ﬁrst clock cycle, the ﬁrst word of the data burst is written along with the ID bit value of 00. The instruction

word is updated on the last word of a data burst and contains the ID bit value, address and length of the data burst.

The maximum burst length is set by the depth of the data FIFO, which is 64 FIFO lines. The data length in the

Address

Data length

Write Instruction Word

Write Data

ID bits

Write Data Word

Reserved

ID bits

Reserved

F_MC_WCLK

F_MC_WDFIFO_WE

F_MC_WD(73:72)

F_MC_WD(71:0)

F_MC_WIFIFO_WE

F_MC_WI(25:24)

F_MC_WI(23:18)

F_MC_WI(17:0)

MC_WIFIFO_FULL

D0-0

...

D0-31

D1-0

D2-0

D3-0

D4-0

D*1

D*32

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