ORSPI4 datasheet(138/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

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instruction word is provided in terms of FIFO lines. Data length for data associated with A0 is shown to be 32 lines.

The maximum burst length is set by the depth of the data FIFO which is 64 FIFO lines.

Data is presented as 9 bytes in every MC_WCLK cycle. A new data word always begins at bit position 71 and has

a unique 2-bit ID. The transition from one ID value to another indicates the start of a new data burst as shown in

Figure 72. For each burst, the values of the ID ﬁelds in the data word and the instruction word are compared.

The write controller ﬁrst waits for the empty ﬂag from the instruction FIFO to be deasserted and processes the ﬁrst

pending instruction. The core reads the instruction word ﬁrst. Based on the data length, the core starts to read the

appropriate amount of data from the data FIFO. The address and data length are passed to the write controller

state machine. After the last data word has been read from the data FIFO, the core increments the instruction FIFO

address to the next pending instruction.

The 2-bit ID ﬁeld in each data word is compared to the 2-bit ID ﬁeld in the processed instruction to maintain

data/instruction coherency. If the ID ﬁelds in the data and instruction words do not match, an error is sent to a soft-

ware register bit. It is the responsibility of the FPGA to provide the exact amount of data speciﬁed in the data length

ﬁeld of the instruction word.

A programmable FIFO full ﬂag (MC_WDFIFO_FULL) is available to the FPGA for the data FIFO. The FIFO ﬂag

threshold is set by the 4-bit software register ﬁeld MC_FULL_THRESHOLD. If the MC_WDFIFO_FULL ﬂag is pro-

grammed to indicate a truly full condition, the FPGA logic must assure that the FIFO does not overrun and that an

instruction word is written in parallel with the ﬁnal data word of a sequence.

Address Multiplexer (MUX)

Address information to the QDRII SRAM is multiplexed between the write port and the read port. This is possible

since data is always transferred in two-word or four-word bursts (word is 36-bits). Logic in the SRAM supplies the

address least signiﬁcant bits for the two-word burst case and the lower two LSbs in the case of four-word bursts. It

is however, necessary to make sure read and write addresses do not contend for the address bus. This function is

performed by the Address MUX logic based on signals from the Memory Read Controller (MRC) and Memory

Write Controller (MWC).

Figure 74 and Figure 75 show the timing of signals at the QDRII SRAM interface for two-word and four-word reads

and writes. The burst size is selectable through the ﬁeld MC_BURST_MODE in the conﬁguration registers

30B03[0]. Write data is sent on the ﬁrst rising edge of the positive clock signal (K), after the write address is pro-

vided. Read data is returned on the second rising edge of K, after the read address is provided. If a sequence of

read and write addresses is sent, both read data and write data are available simultaneously. It is this feature that

gives the QDRII SRAM its high throughput.

Note: Except for one address signal, there is no requirement that PMIA address signals be connected to a particu-

lar address input on the QDRII SRAM, since writes and reads share the one and only address bus. The only excep-

tion is PMIA17, which is only used in 2-word mode, and thus must be connected to the corresponding QDRII

SRAM address input that is only present on the 2-word device (if 2-word/4-word compatibility is to be maintained).

Flexibility in assigning these signals can be useful in optimizing the layout of this bus.

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