ORSPI4 datasheet(140/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

140

Write Controller and Write Data DEMUX

The write timing shown in Figure 74 and Figure 75 is generated by the Memory Write Controller (MWC) logic based

on instruction and status signals from the write FIFOs and synchronization information from the Memory Read

Controller (MRC). The MWC has two functions. First it will read the instruction words from the instruction FIFO and

separate the bit ﬁelds into address, ID and Data length. Then it will generate write cycle timing based on the type of

memory conﬁgured (2 or 4 word burst).

The MWC will also do data/instruction data coherency (ID) checking and generate an error (output

MC_ID_STATUS) if the test fails. The write controllers run at 2x the clock rate (MCLCKx2) in order to generate the

QDRII SRAM data and address timing correctly in relation to the differential memory clock (K, K#). The MWC must

also arbitrate with the MRC to ensure that there is no contention between SRAM read and write cycles, as dis-

cussed in the previous section.

The MWC generates enables to initiate burst writes. Separate read and write address counters are required and

are loaded by the controllers with the content of the address ﬁeld in the instruction word. In order to support 512k x

36 RAM in 2-word burst mode, 18 active address lines are required, whereas in 4-word burst mode, 17 are

required. Data to the QDRII SRAM must also be demultiplexed (DEMUX) by the Write Data DEMUX block in order

to convert from the MC internal format of 72 bit buses to the 36-bit DDR format for the QDR SRAM.

Read Data Capture, MUX and Read Controller

The read timing shown in Figure 74 and Figure 75 is generated by the Memory Read Controller (MRC) logic, based

on information from the read instruction FIFO. The MRC has two functions. First it will read the instruction words

from the instruction FIFO and separate the bit ﬁelds into address and data length information. Then it will generate

read cycle timing, based on the type of memory conﬁgured (2 or 4 word burst) and provide synchronization infor-

mation to the Memory Write Controller (MWC).

The read controller generates enables to initiate the read cycle. A separate read address counters is required and

is loaded by the controller with the content of the address ﬁeld in the instruction word. As was true with the MWR,

to support 512k x 36 RAM in two word burst mode, 17 active address lines are required, whereas in 4-word burst

mode, 18 are required. Data from the QDR RAM must also be multiplexed (MUX) in order to convert to the MC

internal format of 72 bit buses from the 36-bit DDR format for the QDRII SRAM.

In order to capture the SRAM read data the echo clocks (CQ, CQ#) generated by the SRAM are used to latch the

data. This is the most robust and ﬂexible of schemes available to capture the data, as with this source synchronous

technique, the impact of round trip delays from the data leaving the Memory Controller, to data being received back

can be minimized. The outputs of the capture latches are retimed back into the MCLK2x domain in order to be writ-

ten to the Read Data FIFO (RDFIFO) discussed in the next section.

Read Data and Instruction FIFOs

The Read Data FIFO (RDFIFO) is used to store the data that is returned from the QDRII SRAM. It is asynchro-

nously read by logic in the FPGA. The RDFIFO size is 64 X 72 bits.

The Read Instruction FIFO (RIFIFO) is similar to the WIFIFO and is conﬁgured 4 by 32 bits respectively in order to

store up to 4 instructions that are written to the MC by logic in the FPGA. The instruction ﬁelds are data length

(number of cache lines to read) and address (for QDR memory). The read instruction and data word formats are

shown in Figure 76 and Figure 77 respectively.

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