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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ORSPI4 датащи(PDF) 135 Page - Lattice Semiconductor |
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ORSPI4 датащи(HTML) 135 Page - Lattice Semiconductor |
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135 / 263 page  Lattice Semiconductor ORCA ORSPI4 Data Sheet 135 Memory Controller Functional Description The ORSPI4 device includes a Memory Controller interface to an external second generation Quad Data Rate (QDRII) memory. This is provided for additional data buffering beyond the embedded DPRAMs. In this case, the embedded DPRAMs are used as clock-crossing domain FIFOs. The key requirement for this memory interface is the support of a throughput of greater than 20 Gbits/s so that all the data received on the SPI4 interface at 10 Gbits/s can be buffered. A QDRII SRAM supports this throughput with 32 unidirectional data lines. A 36-bit inter- face is provided to allow for parity or control bits to be added. The controller block provides the ability to access an external QDRII SRAM through the FPGA. A set of 72 input data and 72 output data signals are available across the core-FPGA interface. Of the 72 signals, eight can be used either for parity or for data. The core passes the data transparently to and from the QDRII SRAM in two-word or four-word bursts. The data interfaces to memory are 36 bits wide and the address bus is 18 bits wide. This supports the interfaces required for a 512K x 36 bit (18 Mbit) QDRII SRAM. The basic blocks of the Memory Controller are: • FIFOs for Write Data and Instructions • FIFOs for Read Data and Instructions • Read and Write Controllers (including FIFO and memory interface state machines) • Address Multiplexer (MUX) • Write Data DEMUX and Read Data Capture/MUX Blocks A logical block diagram of the Memory Controller is shown in Figure 71. Details of the individual blocks are outlined in the following sections. The blocks are described in sequence for a write from the FPGA and a subsequent read to the FPGA. Figure 71. ORSPI4 QDRII Memory Controller Block Diagram. Write Data FIFO Read Data FIFO Read Instruction FIFO Write Instruction FIFO Full Full Full Empty 74 32 32 72 Write Controller Read Controller Address Mux Write Data Demux Read Data Mux/ Capture 72 72 36 36 18 18 18 Read Clock Write Clock Empty RE Empty RE Empty RE WE Full FPGA Logic QDRII SDRAM Clock Select #1 PLL COUT = CIN * N/M Clock Select #2 MCREFCLK ATREFCLK BTREFCLK COUT = CIN / 2 Write Enable Read Enable Enable Enable WE WE WE RE 74 32 32 PMIC W# R# Q CQ SA D K F_MC_REFCLK MC_SYSCLK F_MC_WD MC_WDFIFO_FULL F_MC_WDFIFO_WE F_MC_WCLK F_MC_WI MC_WIFIFO_FULL F_MC_WIFIFO_WE F_MC_RI MC_RIFIFO_FULL F_MC_RIFIFO_WE F_MC_RCLK MC_RD MC_RDFIFO_EMPTY F_MC_RDFIFO_RE PMIQ PMIA PMIWN PMIK PMIRN PMID FPGA_RESET_MC ORSPI4 QDR II Core ORSPI4 Device External Memory 2 RST RST RST RST RST RST RST RST RST |
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