ORSPI4 datasheet(131/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

131

SERDES Receive Interface in Channel Bypass Mode

Figure 69. Data: MRWD[A:D][39:0]

Clock: RWCK[A:D]

Test Modes

In addition to the operational logic described in the preceding sections, the SERDES contains logic to support var-

ious test modes - both for device validation and evaluation and for operating system level tests. The following sec-

tions discuss two of the test support logic blocks, supporting various loopback modes, in addition to SERDES

characterization pins.

Loopback Testing

Loopback testing is performed by looping back (either internal to the SERDES, by conﬁguring the FPGA logic or by

external connections) transmitted data to the corresponding receiver inputs, or received data to the transmitter out-

put. The loopback path may be either serial or parallel.

In general, loopback tests can be classiﬁed as “near end” or “far end”. In “near end” loopback (Figure 70(a)), data is

generated and checked locally, i.e. by logic on, or connection of, test equipment to the same card as the FPSC. In

“far end” loopback (Figure 70(b)), the generating and checking functions are performed remotely, either by test

equipment or a remote system card.

2.5 / 0.7 ns

FPGA

Embedded Core

1.4/ 0.4 ns

Total prop = 3.4 / 0.85 ns

NOTE: Delays represent average max/min values, not absolute values

÷4

RCK78[A:D]

C RWCK[A:D]

RECOVERED

311MHz

_SERDES_CLK

Delay

Actual delay values are used by

ispLEVER

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