TMS320VC5509 datasheet(97/124 Pages) TI

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Electrical Specifications

April 2001 − Revised January 2008

SPRS163H

5.13 TIN/TOUT Timings (Timer0 Only)

Table 5−23 and Table 5−24 assume testing over recommended operating conditions (see Figure 5−21 and

Figure 5−22).

Table 5−23. TIN/TOUT Pins Configured as Inputs Timing Requirements†‡

NO.

MIN

MAX

UNIT

tw(TIN/TOUTL)

Pulse width, TIN/TOUT low

2P + 1

tw(TIN/TOUTH)

Pulse width, TIN/TOUT high

2P + 1

† P = 1/CPU clock frequency. For example, when running parts at 144 MHz, use P = 6.94 ns.

‡ Only the Timer0 signal is externally available. The Timer1 signal is internally terminated and is not available for external use.

Table 5−24. TIN/TOUT Pins Configured as Outputs Switching Characteristics†‡§

NO.

PARAMETER

MIN

MAX

UNIT

td(COH-TIN/TOUTH)

Delay time, CLKOUT high to TIN/TOUT high

td(COH-TIN/TOUTL)

Delay time, CLKOUT high to TIN/TOUT low

tw(TIN/TOUT)

Pulse duration, TIN/TOUT (output)

P − 1

† P = 1/CPU clock frequency. For example, when running parts at 144 MHz, use P = 6.94 ns.

‡ Only the Timer0 signal is externally available. The Timer1 signal is internally terminated and is not available for external use.

§ For proper operation of the TIN/TOUT pin configured as an output, the timer period must be configured for at least 4 cycles.

TIN/TOUT

as Input

Figure 5−21. TIN/TOUT Timings When Configured as Inputs

TIN/TOUT

as Output

CLKOUT

Figure 5−22. TIN/TOUT Timings When Configured as Outputs

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