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TMS320VC5509 датащи(PDF) 73 Page - Texas Instruments |
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TMS320VC5509 датащи(HTML) 73 Page - Texas Instruments |
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73 / 124 page ![]() Electrical Specifications 73 April 2001 − Revised January 2008 SPRS163H 5.2 Recommended Operating Conditions (Continued) UNIT MAX NOM MIN X2/CLKIN 2.2 DVDD + 0.3 DN and DP‡ 2.0 VIH High-level input voltage, I/O SDA & SCL: VDD related input levels† 0.7*DVDD DVDD(max) +0.5 V VIH High-level input voltage, I/O All other inputs (including hysteresis inputs) 2.2 DVDD + 0.3 V X2/CLKIN −0.3 0.7 DN and DP‡ 0.8 VIL Low-level input voltage, I/O SDA & SCL: VDD related input levels† −0.5 0.3 * DVDD V VIL Low-level input voltage, I/O All other inputs (including hysteresis inputs) −0.3 0.8 V IOH High-level output current DN and DP‡ (VOH = 2.45 V) −17.0 mA IOH High-level output current All other outputs −4 mA DN and DP‡ (VOL = 0.36 V) 17.0 IOL Low-level output current SDA and SCL† 3 mA IOL Low-level output current All other outputs 4 mA TC Operating case temperature −40 85 _C † The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. Due to the fact that different voltage devices can be connected to the I2C bus, the level of logic 0 (low) and logic 1 (high) are not fixed and depends on the associated VDD. ‡ USB I/O pins DP and DN can tolerate a short circuit at D+ and D− to 0 V or 5 V, as long as the recommended series resistors (see Figure 5−40) are connected between the D+ and DP (package), and the D− and DN (package). Do not apply a short circuit to the USB I/O pins DP and DN in absence of the series resistors. NOTE: USB PLL is powered from the core supply and is susceptible to core power supply ripple. The maximum allowable supply ripple is 1% for 1 Hz to 5 kHz; 1.5% for 5 kHz to 10 MHz; 3% for 10 MHz to 100 MHz, and less than 5% for 100 MHz or greater. |
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