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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5509 датащи(PDF) 53 Page - Texas Instruments |
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TMS320VC5509 датащи(HTML) 53 Page - Texas Instruments |
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53 / 124 page  Functional Overview 53 April 2001 − Revised January 2008 SPRS163H Table 3−20. DMA Configuration Registers PORT ADDRESS (WORD) REGISTER NAME DESCRIPTION RESET VALUE† GLOBAL REGISTER 0x0E00 DMA_GCR[2:0] DMA Global Control Register xxxx xxxx xxxx x000 0x0E03 DMA_GTCR DMA Timeout Control Register CHANNEL #0 REGISTERS 0x0C00 DMA_CSDP0 DMA Channel 0 Source Destination Parameters Register 0000 0000 0000 0000 0x0C01 DMA_CCR0[15:0] DMA Channel 0 Control Register 0000 0000 0000 0000 0x0C02 DMA_CICR0[5:0] DMA Channel 0 Interrupt Control Register xxxx xxxx xx00 0011 0x0C03 DMA_CSR0[6:0] DMA Channel 0 Status Register xxxx xxxx xx00 0000 0x0C04 DMA_CSSA_L0 DMA Channel 0 Source Start Address Register (lower bits) Undefined 0x0C05 DMA_CSSA_U0 DMA Channel 0 Source Start Address Register (upper bits) Undefined 0x0C06 DMA_CDSA_L0 DMA Channel 0 Destination Start Address Register (lower bits) Undefined 0x0C07 DMA_CDSA_U0 DMA Channel 0 Destination Start Address Register (upper bits) Undefined 0x0C08 DMA_CEN0 DMA Channel 0 Element Number Register Undefined 0x0C09 DMA_CFN0 DMA Channel 0 Frame Number Register Undefined 0x0C0A DMA_CFI0 DMA Channel 0 Frame Index Register Undefined 0x0C0B DMA_CEI0 DMA Channel 0 Element Index Register Undefined CHANNEL #1 REGISTERS 0x0C20 DMA_CSDP1 DMA Channel 1 Source Destination Parameters Register 0000 0000 0000 0000 0x0C21 DMA_CCR1[15:0] DMA Channel 1 Control Register 0000 0000 0000 0000 0x0C22 DMA_CICR1[5:0] DMA Channel 1 Interrupt Control Register xxxx xxxx xx00 0011 0x0C23 DMA_CSR1[6:0] DMA Channel 1 Status Register xxxx xxxx xx00 0000 0x0C24 DMA_CSSA_L1 DMA Channel 1 Source Start Address Register (lower bits) Undefined 0x0C25 DMA_CSSA_U1 DMA Channel 1 Source Start Address Register (upper bits) Undefined 0x0C26 DMA_CDSA_L1 DMA Channel 1 Destination Start Address Register (lower bits) Undefined 0x0C27 DMA_CDSA_U1 DMA Channel 1 Destination Start Address Register (upper bits) Undefined 0x0C28 DMA_CEN1 DMA Channel 1 Element Number Register Undefined 0x0C29 DMA_CFN1 DMA Channel 1 Frame Number Register Undefined 0x0C2A DMA_CFI1 DMA Channel 1 Frame Index Register Undefined 0x0C2B DMA_CEI1 DMA Channel 1 Element Index Register Undefined CHANNEL #2 REGISTERS 0x0C40 DMA_CSDP2 DMA Channel 2 Source Destination Parameters Register 0000 0000 0000 0000 0x0C41 DMA_CCR2[15:0] DMA Channel 2 Control Register 0000 0000 0000 0000 0x0C42 DMA_CICR2[5:0] DMA Channel 2 Interrupt Control Register xxxx xxxx xx00 0011 † Hardware reset; x denotes a “don’t care.” |
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