TMS320VC5509 datasheet(39/124 Pages) TI

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Functional Overview

April 2001 − Revised January 2008

SPRS163H

Table 3−4. Synchronization Control Function (Continued)

SYNC FIELD IN

DMA_CCR

SYNCHRONIZATION MODE

01010b

McBSP2/MMC−SD2 Transmit Event

Serial Port 2 Mode:

00 = McBSP2 Transmit Event (XEVT2)

01 = MMC/SD2 Transmit Event (XMMCEVT2)

10 = Reserved

11 = Reserved

01011b

Reserved. These bits should always be written with 0.

01100b

Reserved. These bits should always be written with 0.

01101b

Timer 0 Interrupt Event

01110b

Timer 1 Interrupt Event

01111b

External Interrupt 0

10000b

External Interrupt 1

10001b

External Interrupt 2

10010b

External Interrupt 3

10011b

External Interrupt 4 / I2C Receive Event (REVTI2C)†

10100b

I2C Transmit Event (XEVTI2C)

Other values

Reserved (Do not use these values)

† The I2C receive event (REVTI2C) and external interrupt 4 (INT4) share a synchronization input to the DMA. When the SYNC field of the

DMA_CCR is set to 10011b, the logical OR of these two sources is used for DMA synchronization.

3.4

I2C Interface

The TMS320VC5509 includes an I2C serial port. The I2C port supports:

•

Compatible with Philips I2C Specification Revision 2.1 (January 2000)

•

Operates at 100 Kbps or 400 Kbps

•

7-bit addressing mode

•

Master (transmit/receive) and slave (transmit/receive) modes of operation

•

Events: DMA, interrupt, or polling

The I2C module clock must be in the range from 7 MHz to 12 MHz. This is necessary for proper operation of

the I2C module. With the I2C module clock in this range, the noise filters on the SDA and SCL pins suppress

noise that has a duration of 50 ns or shorter. The I2C module clock is derived from the DSP clock divided by

a programmable prescaler.

NOTE:

I/O buffers are not fail-safe. The SDA and SCL pins could potentially draw current if the

device is powered down and SDA and SCL are driven by other devices connected to the I2C bus.

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