CDCE72010 datasheet(12/70 Pages) TI

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AC/DC CHARACTERISTICS (CONTINUED)

CDCE72010

SCAS858 – JUNE 2008...................................................................................................................................................................................................... www.ti.com

over the specified industrial temperature range of –40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

LVPECL Output

fclk

Output frequency

Open loop config.

1500

MHz

LVPECL high-level output

VOH

Load, see Figure 5

VCC – 1.06

VCC – 0.88

voltage

LVPECL low-level output

VOL

Load, see Figure 5

VCC – 2.02

VCC – 1.58

voltage

|VOD|

Differential output voltage

Load, see Figure 5

610

970

Reference to output

VCXO at 491.52MHz, Output 1 is divide by

phase offset without using 16 and reference at 30.72MHz, M and N

tpho

(2)

available delay

delays are fixed to one value (set to 0), PFD:

adjustment

240kHz, (M and N = 128)

tpd(LH)/

Propagation delay time,

Crosspoint to crosspoint, load, see Figure 5

3.4

tpd(HL)

VCXO_IN to output

Divide by 1 for all dividers

Divide by 16 for all dividers

tsk(o)

(3)

LVPECL output skew

Divide by 1 for divider 1

2700

Divide by 16 for all other dividers

Output capacitance on Y0

VCC = 3.3 V; VO = 0 V or VCC

to Y8

Output capacitance on Y9 VCC = 3.3 V; VO = 0 V or VCC

Power-down output

IOPDH

VO = VCC

µA

current

Power-down output

IOPDL

VO = 0 V

µA

current

Duty cycle

tr/tf

Rise and fall time

20% to 80% of Voutpp

135

LVDS-TO-LVPECL

Output skew between

tskP_C

LVDS and LVPECL

Crosspoint to VCC/2;

0.9

1.1

1.3

outputs

LVCMOS-TO-LVPECL

Output skew between

tskP_C

LVCMOS and LVPECL

Crosspoint to VCC/2;

–150

260

700

outputs(4)

(1)

All typical values are at VCC = 3.3 V, TA = 25°C.

(2)

This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and

VCXO delay N).

(3)

The tsk(o) specification is only valid for equal loading of all outputs. :

(4)

Operating the LVCMOS or LVPECL outputs above the maximum frequency will not cause a malfunction to the device, but the output

signal swing might no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS.

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