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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CDCE72010 датащи(PDF) 44 Page - Texas Instruments |
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CDCE72010 датащи(HTML) 44 Page - Texas Instruments |
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44 / 70 page  CDCE72010 SCAS858 – JUNE 2008...................................................................................................................................................................................................... www.ti.com Register 8: CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION 0 A0 Address 0 0 1 A1 Address 1 0 2 A2 Address 2 0 3 A3 Address 3 1 4 0 VCXOBUFSELX VCXO and AUX Input Buffer Type Select (LVPECL,LVDS or LVCMOS) 5 1 VCXOBUFSELY XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin VCXO and AUX 6 2 VCXOACDCSEL Input Buffers If Set to 0 AC Termination, If set to 1 DC Termination EEPROM VCXO Input Buffer 7 3 VCXOHYSTEN If Set to 1 Input Buffers Hysteresis enabled 8 4 VCXOTERMSEL If Set to 0 Input Buffer Internal Termination enabled 9 5 VCXOINVBB VCXO Input Buffer If Set to 1 It biases VCXO Input negative pin with internal VCXOVBB voltage EEPROM 10 6 PH8ADJC0 11 7 PH8ADJC1 12 8 PH8ADJC2 13 9 PH8ADJC3 Output 8 and 9 Coarse phase adjust select for output divider 8 and 9 EEPROM 14 10 PH8ADJC4 15 11 PH8ADJC5 16 12 PH8ADJC6 17 13 OUT8DIVRSEL0 18 14 OUT8DIVRSEL1 19 15 OUT8DIVRSEL2 OUTPUT DIVIDER 8 and 9 Ratio Select 20 16 OUT8DIVRSEL3 Output 8 and 9 EEPROM (See Table 7) 21 17 OUT8DIVRSEL4 22 18 OUT8DIVRSEL5 23 19 OUT8DIVRSEL6 When set to 0, the divider is disabled 24 20 EN89DIV Output 8 and 9 EEPROM When set to 1, the divider is enabled 25 21 PECL8HISWING Output 8 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM CD1 PIN is high and DIVPHA8CD1H is set to low Loads Output Divider 8 and Phase Adjust 8 into OUTPUT 8 26 22 DIVPHA8CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA8CD1H is set to high Loads Output Divider 7 and Phase Adjust 7 into OUTPUT 8 CD1 PIN is low and DIVPHA8CD1L is set to low Loads Output Divider 8 and Phase Adjust 8 into OUTPUT 8 27 23 DIVPHA8CD1L CD1 Low EEPROM CD1 PIN is low and DIVPHA8CD1L is set to high Loads Output Divider 7 and Phase Adjust 7 into OUTPUT 8 28 24 OUTBUF8CD2LX Output Buffer 8 Signaling Selection when CD2 in low CD2 Low EEPROM (X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable 29 25 OUTBUF8CD2LY 30 26 OUTBUF8CD2HX Output Buffer 8 Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable 31 27 OUTBUF8CD2HY 44 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): CDCE72010 |
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