CDCE72010 datasheet(48/70 Pages) TI

48 / 70 page

INTERFACE, CONFIGURATION, AND CONTROL

RAMRegisters

EEPROMCells

Interface&Control

ControlSignals

SPI

UNIVERSAL INPUT AND REFERENCE CLOCK BUFFERS

50W

VBB

PRI_REF

SEC_REF

::INBUFSEL

::ACDCSEL

(AC=1,DC=0)

TERMSEL::

PRIINVBB::

50W

SECINVBB::

CDCE72010

SCAS858 – JUNE 2008...................................................................................................................................................................................................... www.ti.com

The CDCE72010 is designed to support various applications with SPI bus interface and without. In the case

where systems lack the SPI bus or a Boot up configuration is required at start up before the management layer is

up the built in EEPROM is used to provide this function.

The Interface bus takes the serialized address and data and writes to the specified RAM bits. The content of the

RAM bits are connected to logical functions in the device. Changing the content of the RAM bits (high or low)

instantly changes the logical functions inside the device.

At power up or after power down is de-asserted the contents of the EEPROM bits are copied to their

corresponding RAM bits. After that the content of RAM can be changed via the SPI bus. When writing to

EEPROM commands are detected on the SPI bus the control logic begins writing the content of the RAM bits

into the corresponding EEPROM bits. This process takes about 50ms. During this time the power supply should

be above 3.2V.

Figure 15. Interface Control

The CDCE72010 is designed to support what is referred to as a Universal Input Buffer structure. This type of

buffer is designed to accept Differential or single ended inputs and it is sensitive enough to act as a LVPECL or

LVDS in differential mode and LVCMOS in Single ended mode. With the proper external termination various

types of inputs signals can be supported. Those inputs will be discussed in a separate document (application

Notes).

The CDCE72010 has two internal voltage biasing circuitries. One to set the termination voltage for references

(PRI_REF and SEC_REF) and the second biasing circuitry is to set the termination voltage to the VCXO_IN and

AUX_IN. This means that we can only have one type of differential signal on PRI_REF and SEC_REF and only

one type of differential signal on VCXO_IN and AUX_IN.

Figure 16. PRI_REF AND SEC_REF Voltage Biasing Circuitry

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