CDCE72010 datasheet(36/70 Pages) TI

36 / 70 page

CDCE72010

SCAS858 – JUNE 2008...................................................................................................................................................................................................... www.ti.com

SPI

RAM

POWER UP

BIT NAME

DESCRIPTION/FUNCTION

BIT

BLOCK

CONDITION

Address 0

Address 1

Address 2

Address 3

INBUFSELX

Reference Input

Primary and Secondary Buffer Type Select (LVPECL,LVDS or LVCMOS)

EEPROM

Buffers

XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin

INBUFSELY

PRISEL

When REFSELCNTRL is set to 1 the following settings apply:

If RAM Bit (2,3): 00 – no Input Buffer is selected/active

Reference Input

If RAM Bit (2,3): 10 – PRI_BUF is selected, SEC_BUF is powered down

EEPROM

Buffer

SECSEL

If RAM Bit (2,3): 01 – SEC_BUF is selected, PRI_BUF is powered down

If RAM Bit (2,3): 11 – Auto Select (PRI then SEC).

When set to 0, PRI- or SEC-Clocks are selected, depending on Bits 2 and 3

Divider START

VCXOSEL

(default)

EEPROM

DETERM-Block

When set to 1, VCXO/AUX-clock selected, overwrites Bits 2 and 3

Reference Select Control to select if the control of the reference is from the

internal bit in Register 0 RAM bits 2 and 3 or from the external select pin.

- When set to 0: The external pin REF_SEL takes over the selection between

Reference

REFSELCNTRL

PRI and SEC. Autoselect is not available.

EEPROM

Selection Control

- When set to 1: The external pin REF_SEL is ignored. The Table in (Register 0

<2 and 3> ) describes, which reference input clock is selected and available at

(none, PRI, SEC or Autoselect). In autoselect mode, refer to the timing diagram

DELAY_PFD0

PFD

PFD Pulse Width PFD Bit 0

EEPROM

DELAY_PFD1

PFD

PFD Pulse Width PFD Bit 1

EEPROM

CP_MODE

Selects 3V option [0] or 5V option [1]

EEPROM

Charge Pump

Determines in which direction CP current will regulate (Reference Clock leads to

CP_DIR

EEPROM

Feedback Clock; Positive CP output current [0]; Negative CP output current [1]

Switches the current source in the Charge Pump on when set to 1 (TI

CP_SRC

EEPROM

Test-GTME)

Diagnostics

CP_SNK

Switches the current sink in the Charge Pump on when set to 1 (TI Test-GTME)

EEPROM

CP_OPA

Switches the Charge Pump op-amp off when set to 1 (TI Test-GTME)

EEPROM

CP_PRE

Preset Charge Pump output voltage to VCC_CP/2, on [1], off [0]

EEPROM

ICP0

CP Current Setting Bit 0

EEPROM

ICP1

Charge Pump

CP Current Setting Bit 1

EEPROM

ICP2

CP Current Setting Bit 2

EEPROM

ICP3

CP Current Setting Bit 3

EEPROM

RESERVED

EEPROM

RESERVED

EEPROM

Enables the 12k pull-down resistor at I_REF_CP Pin when set to 1 (TI

IREFRES

Diagnostics

EEPROM

Test-GTME)

PECL0HISWING

Output 0

High output voltage swing in LVPECL Mode if set to 1

EEPROM

RESERVED

EEPROM

RESERVED

EEPROM

OUTBUF0CD2LX

Output Buffer 0 Signaling Selection when CD2 In low

CD2 Low

EEPROM

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

OUTBUF0CD2LY

OUTBUF0CD2HX

Output Buffer 0 Signaling Selection when CD2 in high

CD2 High

EEPROM

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: output disable

OUTBUF0CD2HY

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