CDCE72010 datasheet(47/70 Pages) TI

47 / 70 page

CDCE72010

www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008

Register11: CD Mode

SPI

RAM

POWER UP

BIT NAME

DESCRIPTION/FUNCTION

BIT

BLOCK

CONDITION

Address 0

Address 1

Address 2

Address 3

PRI_DIV2

Input Buffers

If set to 1 Enables Primary Reference Divide by 2

EEPROM

SEC_DIV2

Input Buffers

If set to 1 Enables Secondary Reference Divide by 2

EEPROM

FB Path Integer

When set to 0, FB divider is active

FB_DIS

EEPROM

Counter 32

When set to 1, FB divider is disabled

FB Path Integer

When set to 0, FB clock is CMOS type

FB_CML_SEL

EEPROM

Counter 32

When set to 1, FB clock is CML type and uses CML2CMOS converter in PLL

FB-Divider /

When set to 0, Input clock for FB not inverted (normal mode, low speed)

FB_INCLK_INV

Deterministic

EEPROM

When set to 1, Input clock for FB inverted (higher speed mode)

Blocks

FB_COUNT32_0

Feedback Counter Bit0

FB_COUNT32_1

Feedback Counter Bit1

FB_COUNT32_2

Feedback Counter Bit2

FB Path Integer

FB_COUNT32_3

Counter 32

Feedback Counter Bit3

EEPROM

(P divider)

FB_COUNT32_4

Feedback Counter Bit4

FB_COUNT32_5

Feedback Counter Bit5

FB_COUNT32_6

Feedback Counter Bit6

FB_PHASE0

Feedback Phase Adjust Bit0

FB_PHASE1

Feedback Phase Adjust Bit1

FB_PHASE2

Feedback Phase Adjust Bit2

FB Path Integer

FB_PHASE3

Counter 32

Feedback Phase Adjust Bit3

EEPROM

(P Divider)

FB_PHASE4

Feedback Phase Adjust Bit4

FB_PHASE5

Feedback Phase Adjust Bit5

FB_PHASE6

Feedback Phase Adjust Bit6

If set to 0, PLL is in normal mode

PD_PLL

PLL

EEPROM

If set to 1, PLL is powered down

Clock Tree and

FB_MUX_SEL

When set to 0, the VCXO Clock is selected for the Clock Tree and FB-Div/Det

Deterministic

EEPROM

Table 8

When set to 1, the AUX Clock is selected for the Clock Tree and FB-Div/Det.

Block

OUT_MUX_SEL

If Set to 0 it selects the VCXO Clock and if Set to 1 it selects the AUX Clock

EEPROM

Table 8

Feed Back Path Selects FB/VCXO-Path when set to 0 (TI Test-GTME)

FB_SEL

Diagnostics

EEPROM

The Secondary Reference clock input is selected when set to 1 (TI Test-GTME)

NRESHAPE1

Reshapes the Reference Clock Signal 0, Disable Reshape 1

Reference

EEPROM

If set to 0 it enables short delay for fast operation

Selection Control

SEL_DEL1

If Set to 1 Long Delay recommended for input references below 150Mhz.

RESET_HOLD

Reset Circuitry

If set to 1 the RESET or HOLD pin acts as HOLD, set to 0 it acts as RESET.

EEPROM

EPUNLOCK

Status

EEPROM Unlock

EEPROM

EPSTATUS

Status

EEPROM Status

EEPROM

Table 8. Output Buffers Source Feed, PLL Source Feed, and AUX IN/OUTPUT 9 Selection

FB_MUX_SEL

OUT_MUX_SEL

PLL FEED AND OUTPUT FEED

AUX INPUT OR OUTPUT 9

VCXO::PLL, VCXO::Y0…Y9 and Deterministic Block

OUTPUT 9 is Enabled(1)

AUXIN::PLL, VCXO::Y0…Y8 and Deterministic Block

AUX IN is Enabled

VCXO::PLL, AUXIN::Y0…Y8 and Deterministic Block

AUX IN is Enabled

AUXIN::PLL, AUXIN::Y0…Y8 and Deterministic Block

AUX IN is Enabled

(1)

Default

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