CDCE72010 datasheet(45/70 Pages) TI

45 / 70 page

CDCE72010

www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008

SPI

RAM

POWER UP

BIT NAME

DESCRIPTION/FUNCTION

BIT

BLOCK

CONDITION

Address 0

Address 1

Address 2

Address 3

HOLDF1

Enables the Frequency Hold-Over Function 1 on 1, off 0

HOLDF2

Enables the Frequency Hold-Over Function 2 on 1, off 0

HOLD

3-State Charge Pump 0 - (equal to HOLD-Pin function)

HOLD function always activated “1” (recommended for test purposes, only)

HOLD- Over

EEPROM

Triggered by analog PLL Lock detect outputs

HOLDTR

If analog PLL Lock Signal is [1] (PLL locked), HOLD is activated

If analog PLL Lock Signal is [0] (PLL not lock), HOLD is deactivated

HOLD_CNT0

HOLD1 Function is reactivated after X Ref Clock Cycles. Defined by

(HOLD_CNT0,HOLD_CNT1)::X= Number of Clock Cycles.

HOLD_CNT1

For (00)::X=64, (01) ::X=128, (10)::X=256, (11)::X=512 Clock Cycles.

LOCKW 2

Extended Lock-detect window Bit 2 (Also refer to Reg 7 RAM Bits 0 and 1)

LOCK-DET

EEPROM

LOCKW 3

Extended Lock-detect window Bit 3 (Also refer to Reg 7 RAM Bits 0 and 1)

NOINV_RESHOL_IN

When set to 0, SPI/HOLD_INT and SPI/RESET_INT inverted (default)

Chip CORE

EEPROM

When set to 1, SPI/HOLD_INT and SPI/RESET_INT not inverted

When GTME = 0, this bit has no functionality, But when GTME = 1, then:

Diagnostic: PLL

DIVSYNC_DIS

When set to 0, START-Signal is synchronized to N/M Divider Input Clocks

EEPROM

N/M Divider

When set to 1, START-Sync N/M Divider in PLL are bypassed

Divider START

When set to 0, START-Signal is synchronized to VCXO-Clock

START_BYPASS

EEPROM

DETERM-Block

When set to 1, START-Sync Block is bypassed

Divider START

When set to 0, Sync Logic active when VCXO/AUX-Clocks are available

INDET_BP

EEPROM

DETERM-Block

When set to 1, Sync Logic is independent from VCXO- and/or AUX-Clocks

Divider START

When set to 0, Sync Logic waits for 1st PLL_LOCK state

PLL_LOCK_BP

EEPROM

DETERM-Block

When set to 1, Sync Logic independent from 1st PLL_LOCK

When set to 0, Sync Logic is independent from VCXO/DIV_FB freq. (PLL-FD)

Divider START

LOW_FD_FB_EN

When set to 1, Sync Logic is started for VCXO/DIV_FB > ~600KHz,

EEPROM

DETERM-Block

stopped for VCXO/DIV_FB < ~600KHz

PLL

When set to 0, M-Divider uses NHOLD1 as NPRESET

NPRESET_MDIV

EEPROM

M/FB-Divider

When set to 1, M-Divider NOT preseted by NHOLD1

BIAS_DIV_FB<0>

When BIAS_DIV_FB<1:0> =

Feedback

00, No current reduction for FB-Divider

EEPROM

Divider

01, Current reduction for FB-Divider by about 20%

BIAS_DIV_FB<1>

10, Current reduction for FB-Divider by about 30%

BIAS_DIV89<0>

When BIAS_DIV89<1:0> =

Output Divider

00, No current reduction for all output-divider

EEPROM

8 and 9

01, Current reduction for all output-divider by about 20%

BIAS_DIV89<1>

10, Current reduction for all output-divider by about 30%

AUXINVBB

If Set to 1 it Biases AUX Input Negative Pin with internal VCXOVBB voltage.

AUX Buffer

EEPROM

If Set to 1 AUX in input Mode Buffer is disabled. If Set to 0 it follows the

DIS_AUX_Y9

behavior of FB_MUX_SEL and OUT_MUX_SEL bits settings.

PECL9HISWING

Output 9

High Output Voltage Swing in LVPECL Mode if set to 1

EEPROM

RESERVED

EEPROM

RESERVED

EEPROM

OUTBUF9CD2LX

Output Buffer 9 Signaling Selection when CD2 in low

CD2 Low

EEPROM

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

OUTBUF9CD2LY

OUTBUF9CD2HX

Output Buffer 9 Signaling Selection when CD2 in high

CD2 High

EEPROM

(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable

OUTBUF9CD2HY

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