CE6313 datasheet(22/24 Pages) INTEL

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CE6313

Data Sheet

Intel Corporation

Sleep

Stops oscillator and sets minimum power levels to

entire device (except ADCs - register controlled

power-down)

ICMOS

3.3

CLK1

Primary 2-wire serial bus clock

CMOS1

DATA1

Primary 2-wire serial bus data

I/O

Open

drain1

DATA2

Secondary 2-wire bus data to tuner front end. Also

usable as GPP1 (general purpose port pin) for other

purposes.

I/O

Open

drain1

CLK2

Secondary 2-wire bus clock to tuner front end. Also

usable as GPP0 (general purpose port pin) for other

purposes.

I/O

Open

drain1

OscMode

Controls oscillator mode to suit crystal or external

signal

CMOS

3.3

XTI

Crystal input or external reference clock input

CMOS

1.8

XTO

Crystal output, includes internal feedback resistor to

XTI

I/O

CMOS

1.8

Iin

I channel input

analog

Iin

I channel negative input

analog

Qin

Q channel negative input

analog

Qin

Q channel input

analog

35,36,37

ADDR[1:4]

Primary 2-wire bus address defining pins

CMOS

3.3

AGC

AGC sigma-delta output (acts as input only in

production test modes)

I/O

Open

drain1

Test

For normal operation, this pin must be held at 0 V.

CMOS

3.3

IRQ

Active low interrupt output. Reading all active

interrupt registers resets this pin. Can also be defined

as MICLK - external clock input for MPEG data

I/O

Open

drain1

MOSTRT

MPEG output start signal. High during the first byte of

a packet.

OCMOS

Tri-state

3.3

MOVAL

MPEG data output valid. High during the MOCLK

cycles when valid data bytes are being output.

OCMOS

Tri-state

3.3

48,49,52

,53,56,

57,60,61

MDO[0:7]

MPEG transport packet data output bus. Can be tri-

stated under control of a register bit.

OCMOS

Tri-state

3.3

MOCLK

MPEG clock output at the data byte rate.

CMOS

Tri-state

3.3

Pin Description Table (continued)

Name

Description

I/O

Note

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