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Intel Corporation

D55751-001

Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

Copyright © 2006 Intel Corporation. All rights reserved.

Features

• Conforms to EBU specification for DVB-S and

DirecTV specification for DSS

• On-chip digital filtering supports 1 - 45 MSps

symbol rates

• On-chip 60 or 90 MHz dual-ADC

• High speed scanning mode for blind symbol

rate/code rate acquisition

• Automatic spectral inversion resolution

• High level software interface for minimum

development time

• Up to ±22.5 MHz LNB frequency tracking

• DiSEqC™ v2.2: receive/transmit for full control of

LNB, dish and other components

• Compact 64-pin LQFP package (7 x 7 mm)

• A full DVB-S front-end reference design is

available, ref. CE9541

Applications

• DVB 1 - 45 MSps compliant satellite receivers

• DSS 20 MSps compliant satellite receivers

• SMATV (Single Master Antenna TV) trans-

modulators

• Satellite PC applications

Description

The

CE6313

is

a

QPSK/BPSK

1 - 45 MSps

demodulator and channel decoder for digital satellite

television transmissions to the European Broadcast

Union ETS 300 421 specification. It receives analogue

I and Q signals from the tuner, digitises and digitally

demodulates this signal, implements the complete

DVB/DSS FEC (Forward Error Correction) and de-

scrambling function. The output is in the form of

MPEG2 or DSS transport stream data packets. The

CE6313 also provides automatic gain control to the RF

front-end device.

The CE6313 has a serial 2-wire bus interface to the

control microprocessor. Minimal software is required to

control the CE6313 because of the built in automatic

search and decode control functions.

May 2006

Ordering Information

DJCE6313 882131

64 Pin LQFP Trays

WJCE6313 882207

64 Pin LQFP* Trays

*Pb Free Matte Tin

0

°C to +70°C

CE6313

DVB-S Satellite Demodulator

Data Sheet

Figure 1 - Functional Block Diagram

I I/P

Q I/P

Dual ADC

De-rotator

Decimation

Filtering

Timing recovery

Matched filter

Phase recovery

MPEG/

DSS

Packets

Bus I/O

2-Wire Bus

Interface

Acquisition

Control

Clock Generation

Analog

AGC

Control

DVB

DSS

FEC