CE6313

Data Sheet

16

Intel Corporation

3. Set DiS_Mode[2:0] = 4 to command the CE6313 to encode the data and transmit the message.

4. Reset DiS_Mode[2:0] to either 0 or 1 depending on previous setting of 22 kHz off or on. The data loaded into the

DiSEqC_INSTR register is retained, so that if the same message is to be repeated, stage 1 above can be omit-

ted.

2.6.2

DiSEqC Receiving Messages

The CE6313 will automatically listen for DiSEqC messages 5 ms after a message has been transmitted. If a return

message is expected, the DiS_Mode[2:0] must be set to zero in order to leave the LNB control signal free for

another DiSEqC transmitter to respond. The sequence of events to receive a message are as follows:

1. Ensure that DiSEqC2/GPP2 pin 2 is an input by setting GPP_CTRL register address-20 bit-5 to zero.

2. Enable interrupts if the IRQ pin 43 is used to interrupt the host processor in DiSEqC2_CTRL1 register 121.

3. Monitor DiS_INT register.

4. If bit-3 = 1 and bit-1 = 0, there has been no message received.

5. If a message has been received, bit-0 will be set. If bit-1 is also set the message is complete. DiS_INT register

bits-7-4 indicate how many bytes have been received.

6. Read the received message from DiS_FIFO register 120 by setting the Inhibit Auto Incrementing (IAI) bit-7 in

RADD, the register address byte and sequentially reading DiS_FIFO for the indicated number of bytes. Each

data byte read requires two 2-wire bus reads. The second or the pair of bytes contains the parity bit and a parity

bit error indicator.

The user may choose to wait for the end of message indication, before reading the message, if it is known that the

message is not greater than eight bytes. However, if the length of message is not known, the message should be

read out of the FIFO by the host as it is being received. Care must be taken to avoid a FIFO buffer overflow.

DiS_INT register bits-7-4 will indicate how many bytes remain in the FIFO.

3.0

Microprocessor Control

3.1

RADD: 2-wire Register Address (W)

RADD is the internal 2-wire bus register address. It is the first byte written after the CE6313 2-wire bus address

when in write mode.

To write to the chip, the bus master should send a START condition and the chip address with the write bit set,

followed by the register address where subsequent data bytes are to be written. Finally, when the 'message' has

been sent, a STOP condition is sent to free the bus.

To read from the chip from register address zero, the bus master should send a START condition and the chip

address with the read bit set, followed by the requisite number of clocks to read the bytes out. Finally a STOP

condition is sent to free the bus. RADD is not sent in this case.

To read from the chip from an address other than zero, the bus master should send the chip address with the write

bit set, followed by the register address from where subsequent data bytes are to be read. Then the bus master

should send a repeat START condition and the chip address with the read bit set, followed by the requisite number

of CLK1 clocks to read the required bytes out. Finally a STOP condition is sent to free the bus. A STOP condition

resets the RADD value to 00.