CE6313

Data Sheet

8

Intel Corporation

2.0

Functional Overview

2.1

Introduction

CE6313 is a single-chip variable rate digital QPSK/BPSK satellite demodulator and channel decoder. The CE6313

accepts base-band in-phase and quadrature analogue signals and delivers an MPEG or DSS packet data stream.

Digital filtering in CE6313 removes the need for programmable external anti-alias filtering for all symbol rates from

1 - 45 MSps. Frequency, timing and carrier phase recovery are all digital and the only feed-back to the analogue

front-end is for automatic gain control. The digital phase recovery loop enables very fine bandwidth control that is

needed to overcome performance degradation due to phase and thermal noise.

All acquisition algorithms are built into the CE6313 controller. The CE6313 can be operated in a Command Driven

Control (CDC) mode by specifying the symbol rate and Viterbi code rate. There is also a provision for a search for

unknown symbol rates and Viterbi code rates.

2.2

Analogue-to-Digital Converter

The A/D converters sample single-ended or differential analogue inputs and consist of a dual ADC and circuitry to

provide improved SiNaD (Signal-Noise and Distortion) and channel matching.

The fixed rate sampling clock is provided on-chip using a programmable PLL needing only a low cost 10 to 16 MHz

crystal. Different crystal frequencies can be combined with different PLL ratios, depending on the maximum symbol

rate, allowing a very flexible approach to clock generation. An external clock signal in the range 4 to 16 MHz can

also be used as the master clock.

2.3

QPSK Demodulator

The demodulator in the CE6313 consists of signal amplitude offset compensation, frequency offset compensation,

decimation filtering, carrier recovery, symbol recovery and matched filtering. The decimation filters give continuous

operation from 2 Mbps to 90 Mbps allowing one receiver to cover the needs of the consumer market as well as the

single carrier per channel (SCPC) market with the same components without compromising performance, that is,

the channel reception is within 0.5 dB from theory. For a given symbol rate, control algorithms on the chip detect the

number of decimation stages needed and switch them in automatically.

The frequency offset compensation circuitry is capable of tracking out up to ±22.5 MHz frequency offset. This

allows the system to cope with relatively large frequency uncertainties introduced by the Low Noise Block (LNB).

Full control of the LNB is provided by the DiSEqC outputs from the CE6313. Horizontal/vertical polarization and an

instruction modulated 22 kHz signal are available under register control. All DiSEqC functions are implemented on

the CE6313. An internal state machine that handles all the demodulator functions controls the signal tracking and

acquisition. Various preset modes are available as well as blind acquisition where the receiver has no prior

knowledge of the received signal. Fast acquisition algorithms have been provided for low symbol rate applications.

Full interactive control of the acquisition function is possible for debug purposes. In the event of a signal fade or a

cycle slip, the QPSK demodulator allows sufficient time for the FEC to reacquire lock, for example, via a phase

rotation in the Viterbi decoder. This is to minimize the loss of signal due to the signal fade. Only if the FEC fails to

re-acquire lock for a long period (which is programmable) the QPSK will try to re-acquire the signal.

The matched filter is a root-raised-cosine filter with either 0.20 or 0.35 roll-off, compliant with DSS and DVB

standards. Although not a part of the DVB standard, CE6313 allows a roll-off of 0.20 to be used with other DVB

parameters. An AGC signal is provided to control the signal levels in the tuner section of the receiver and ensure

the signal level fed to the CE6313 is set at an optimal value under all reception conditions.

The CE6313 provides comprehensive information on the input signal and the state of the various parts of the

device. This information includes signal to noise ratio (SNR), signal level, AGC lock, timing and carrier lock signals.

A maskable interrupt output is available to inform the host controller when events occur.