CE6313

Data Sheet

11

Intel Corporation

Figure 7 - Viterbi Error Count Coarse Indication

2.4.2

The Frame Alignment Block

The frame alignment algorithm detects a sequence of correctly spaced synchronizing bytes in the Viterbi decoded

bit-stream and arranges the input into blocks of data bytes. Each block consists of 204 bytes for DVB and 147 bytes

for DSS. In the DSS mode, the synchronizing byte is removed from the data stream, so only 146 bytes of a block

are passed to the next stage. The frame alignment block also removes the 180° phase ambiguity not removed by

the Viterbi decoder.

2.4.3

The De-Interleaver Block

2.4.3.1

DVB

Before transmission, the data bytes are interleaved with each other in a cyclic pattern of twelve. This ensures the

bytes are spaced out to avoid the possibility of a noise spike corrupting a group of consecutive message bytes.

Figure 8 below shows conceptually how the convolutional de-interleaving system works. The synchronization byte

is always loaded into the First-In-First-Out (FIFO) memory in branch 0. The switch is operated at regular byte

intervals to insert successively received bytes into successive branches. After 12 bytes have been received,

byte 13 is written next to the synchronization byte in branch 0, etc. In the CE6313, this de-interleaving function is

realized using on-chip Random Access Memory (RAM).

VIT_MAXERR[3:0]

Data Bits

Status

VITERBI

Coarse

Bit

Error

Count

0

0