CE6313

Data Sheet

14

Intel Corporation

2.4.5

The Energy Dispersal (de-scrambler) Block, DVB Only

Before Reed-Solomon encoding in the DVB transmission system, the MPEG2 data stream is randomised using the

configuration shown in Figure 12 below. This is a Pseudo Random Binary Sequence (PRBS) generator, with the

polynomial:

The PRBS registers are loaded with the initialisation sequence as shown, at the start of the first transport packet in

a group of eight packets. This point is indicated by the inverted sync byte 0xB8 (the normal DVB sync byte is 0x47).

The data starting with the first byte after the sync byte are randomised by exclusive-ORing data bits with the PRBS

(the sync bytes themselves are not randomised). In the decoder, the process of de-randomising or de-scrambling

the data is exactly the same as described above. The de-scrambler also inverts the sync byte 0xB8 so that all

MPEG output packets have the same sync byte 0x47.

Figure 12 - DVB Energy Dispersal Conceptual Diagram

2.4.6

Output Stage

The transport stream can be output in a byte-parallel or bit-serial mode. The output interface consists of an 8-bit

output, output clock, a packet validation level, a packet start pulse and a block error indicator.

The output clock rate depends on the symbol rate, QPSK/BPSK choice, convolutional (Viterbi) coding rate,

DVB/DSS choice and byte-parallel or bit-serial output mode. This rate is computed by CE6313 to be very close to

the minimum required to output packet data without packet overlap. Furthermore, the packets at the output of

CE6313 are as evenly spaced as possible to minimize packet position movement in the transport layer. The

maximum movement in the packet synchronization byte position is limited to ±1 output clock period.

2.5

Control

Automatic symbol rate search, code rate search, signal acquisition and signal tracking algorithms are built into the

CE6313 using a sophisticated on-chip controller. The software interaction with the device is via a simple Command

Driven Control (CDC) interface. This CDC maps high level inputs such as symbol rates in MSps and frequencies in

MHz, to low level on-chip register settings. The on-chip control state machine and the CDC significantly reduces the

software overhead as well as the channel search times. There is also an option for the host processor to by-pass

both the CDC as well as the on-chip controller and take direct control of the QPSK demodulator. Once the CE6313

has locked to the signal, any frequency offset can be read from the LNB_FREQ error registers 7 and 8. The

frequency synthesiser under the software control can be re-tuned in frequency to optimise the received signal

within the baseband filter bandwidth. Note that CE6313 compensates for any frequency offsets before QPSK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

100

0

0

0000

000

1

11

XOR

Initialisation sequence