CE6313

Data Sheet

17

Intel Corporation

RADD (virtual register, address none)

bit-7:

IAI

High = Inhibit auto increment

Low = Increment addresses

bits 6-0:

AD[6:0]

register address, numbers in the range 0 to 127 are allowed

When the register address is incremented to 127 it stops and the bus will continue to write to or read from register

127 until a STOP condition is sent.

3.2

Primary 2-wire Bus Interface

The primary 2-wire bus serial interface uses pins:

DATA1 (pin 11) serial data, the most significant bit is sent first.

CLK1 (pin 10) serial clock.

The 2-wire bus address is determined by applying Vdd or Gnd to the ADDR[4:1] pins while the three MSBs of the

address are internally set to ‘0’.

For compatibility with earlier devices, the 2-wire bus address will normally be 0001 110 R/W and the pins connected

as follows:

When the CE6313 is powered up, the Reset pin 1 should be maintained low for typically 100 ms after Vdd and

CVdd have reached normal operation levels, and the Sleep pin 9 has gone low. This is to ensure that the crystal

oscillator and internal PLL have become fully established and that the internal reset signal is fully clocked into all

parts of the circuit. As the reset pin is pulled high, the logic levels on Addr[4:1] are latched to become the 2-wire bus

address AD[6:0].

The circuit works as a slave transmitter with the eighth bit set high or as a slave receiver with the eighth bit set low.

In receive mode, the first data byte is written to the RADD virtual register, which forms the register sub-address.

Bit 7 of the RADD register, IAI is an Inhibit Auto Increment function. When the IAI bit is set high, the automatic

incrementing of register addresses is inhibited. IAI set low is the normal situation so that data bytes sent on the

2-wire bus after the RADD register data are loaded into successive registers. This automatic incrementing feature

avoids the need to individually address each register.

Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address

is not recognised, the CE6313 will ignore all activity until a valid chip address is received. The 2-wire bus START

command does NOT reset the RADD register to 00. This allows a combined 2-wire bus message to point to a

particular read register with a write command, followed immediately with a read data command. If required, this

could next be followed with a write command to continue from the latest address. Finally a STOP command should

be sent to free the bus.

When the 2-wire bus is addressed (after a recognised STOP command) with the read bit set, the first byte read out

will be the content of register 00.

NAME

ADR

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-0

Def

hex

RADD

N/A

IAI

AD6

AD5

AD4

AD3

AD2

AD1

AD0

W-

Addr[4]

Addr[3]

Addr[2]

Addr[1]

Vdd

Vdd

Vdd

Gnd