CE6313

Data Sheet

19

Intel Corporation

4.3

Primary 2-Wire Bus Timing

Figure 14 - Primary 2-Wire Bus Timing

Where: S = Start

Sr = Restart, i.e., Start without stopping first.

P = Stop

4.4

Crystal Specification

Parallel resonant fundamental frequency (preferred) 9.99 to 16.01 MHz.

Tolerance over operating temperature range ±25 ppm.

Tolerance overall ±50 ppm.

Table 1 - Primary 2-wire bus timing

Parameter: Primary 2-wire bus only

Symbol

Value

Unit

Min.

Max.

CLK1 clock frequency (for XTI

≥10MHz)

0

400

kHz

Bus free time between a STOP and START condition

1300

ns

Hold time (repeated) START condition

600

ns

LOW period of CLK1 clock

1300

ns

HIGH period of CLK1 clock

600

ns

Set-up time for a repeated START condition

600

ns

Data hold time (when input)

0ns

Data set-up time

100

ns

Rise time of both CLK1 and DATA1 signals

1. Cb = the total capacitance on either clock or data line in pF.

2. The rise time depends on the external bus pull up resistor and bus capacitance.

ns

Fall time of both CLK1 and DATA1 signals, (100pF to ground)

300

ns

Set-up time for a STOP condition

600

ns